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Fix the no-caller-saves bug for MIPS 

Seems that ABI mandates that we allocate space for arg0..4 even if we do
pass them as registers. For some reason write_io_register<> functions
write in that stack area (1 word) corrupting the s0 saved register.
This seems to be a new gcc behaviour?
This commit is contained in:
David Guillen Fandos 2021-06-22 00:09:44 +02:00
parent f8d4276e12
commit dbf72e95ef
2 changed files with 24 additions and 41 deletions
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21
Makefile
View File

@ -375,7 +375,7 @@ else ifeq ($(platform), mips32)
SHARED := -shared -nostdlib -Wl,--version-script=link.T
fpic := -fPIC -DPIC
CFLAGS += -fomit-frame-pointer -ffast-math -march=mips32 -mtune=mips32r2 -mhard-float
CFLAGS += -fno-caller-saves -DMIPS_HAS_R2_INSTS
CFLAGS += -DMIPS_HAS_R2_INSTS
HAVE_DYNAREC := 1
CPU_ARCH := mips
@ -385,7 +385,6 @@ else ifeq ($(platform), mips64n32)
SHARED := -shared -nostdlib -Wl,--version-script=link.T
fpic := -fPIC -DPIC
CFLAGS += -fomit-frame-pointer -ffast-math -march=mips64 -mabi=n32 -mhard-float
CFLAGS += -fno-caller-saves
HAVE_DYNAREC := 1
CPU_ARCH := mips
@ -394,7 +393,7 @@ else ifeq ($(platform), emscripten)
TARGET := $(TARGET_NAME)_libretro_$(platform).bc
STATIC_LINKING = 1
# GCW0
# GCW0 (OD and OD Beta)
else ifeq ($(platform), gcw0)
TARGET := $(TARGET_NAME)_libretro.so
CC = /opt/gcw0-toolchain/usr/bin/mipsel-linux-gcc
@ -407,22 +406,6 @@ else ifeq ($(platform), gcw0)
HAVE_DYNAREC := 1
CPU_ARCH := mips
# GCW0 (OpenDingux Beta)
else ifeq ($(platform), gcw0-odbeta)
TARGET := $(TARGET_NAME)_libretro.so
CC = /opt/gcw0-toolchain/usr/bin/mipsel-linux-gcc
CXX = /opt/gcw0-toolchain/usr/bin/mipsel-linux-g++
AR = /opt/gcw0-toolchain/usr/bin/mipsel-linux-ar
SHARED := -shared -nostdlib -Wl,--version-script=link.T
fpic := -fPIC -DPIC
CFLAGS += -fomit-frame-pointer -ffast-math -march=mips32 -mtune=mips32r2 -mhard-float
# The ASM code and/or MIPS dynarec of GPSP does not respect
# MIPS calling conventions, so we must use '-fno-caller-saves'
# for the OpenDingux Beta build
CFLAGS += -fno-caller-saves -DMIPS_HAS_R2_INSTS
HAVE_DYNAREC := 1
CPU_ARCH := mips
# Windows
else
TARGET := $(TARGET_NAME)_libretro.dll

44
psp/mips_stub.S
View File

@ -293,18 +293,18 @@ mips_cheat_hook:
# ARM regs must be saved before branching here
return_to_main:
REG_L $28, GP_SAVE($16) # Restore previous state
REG_L $s0, 0*SZREG($sp)
REG_L $s1, 1*SZREG($sp)
REG_L $s2, 2*SZREG($sp)
REG_L $s3, 3*SZREG($sp)
REG_L $s4, 4*SZREG($sp)
REG_L $s5, 5*SZREG($sp)
REG_L $s6, 6*SZREG($sp)
REG_L $s7, 7*SZREG($sp)
REG_L $fp, 8*SZREG($sp)
REG_L $ra, 9*SZREG($sp)
REG_L $s0, 4*SZREG($sp)
REG_L $s1, 5*SZREG($sp)
REG_L $s2, 6*SZREG($sp)
REG_L $s3, 7*SZREG($sp)
REG_L $s4, 8*SZREG($sp)
REG_L $s5, 9*SZREG($sp)
REG_L $s6, 10*SZREG($sp)
REG_L $s7, 11*SZREG($sp)
REG_L $fp, 12*SZREG($sp)
REG_L $ra, 13*SZREG($sp)
jr $ra # Return to main
addiu $sp, $sp, 80 # Restore stack pointer (delay slot)
addiu $sp, $sp, 112 # Restore stack pointer (delay slot)
# Perform an indirect branch.
@ -590,17 +590,17 @@ asr_shift_high:
execute_arm_translate_internal:
addiu $sp, $sp, -80 # Store the main thread context
REG_S $s0, 0*SZREG($sp)
REG_S $s1, 1*SZREG($sp)
REG_S $s2, 2*SZREG($sp)
REG_S $s3, 3*SZREG($sp)
REG_S $s4, 4*SZREG($sp)
REG_S $s5, 5*SZREG($sp)
REG_S $s6, 6*SZREG($sp)
REG_S $s7, 7*SZREG($sp)
REG_S $fp, 8*SZREG($sp)
REG_S $ra, 9*SZREG($sp)
addiu $sp, $sp, -112 # Store the main thread context
REG_S $s0, 4*SZREG($sp)
REG_S $s1, 5*SZREG($sp)
REG_S $s2, 6*SZREG($sp)
REG_S $s3, 7*SZREG($sp)
REG_S $s4, 8*SZREG($sp)
REG_S $s5, 9*SZREG($sp)
REG_S $s6, 10*SZREG($sp)
REG_S $s7, 11*SZREG($sp)
REG_S $fp, 12*SZREG($sp)
REG_S $ra, 13*SZREG($sp)
move $16, $5
REG_S $28, GP_SAVE($16)