Fix Vita port and likely some Linux/Android hidden issues
Using an invalid SP makes Vita crash (for an unkown reason) and makes things like C signal handlers crash (luckily Retroarch doesn't use them). It is also a violation of the ABI and not a great idea. Recycled some little used registers to free SP. Perf should be roughly the same.
This commit is contained in:
David Guillen Fandos
David G. F
parent
ff48af07b0
commit
d83f8fbd25
2 changed files with 15 additions and 16 deletions
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@ -67,9 +67,10 @@ void execute_store_u32_safe(u32 address, u32 source);
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#define reg_a1 ARMREG_R1
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#define reg_a2 ARMREG_R2
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/* scratch0 is shared with flags, be careful! */
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#define reg_s0 ARMREG_R9
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#define reg_base ARMREG_SP
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#define reg_flags ARMREG_R11
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#define reg_base ARMREG_R11
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#define reg_flags ARMREG_R9
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#define reg_cycles ARMREG_R12
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@ -110,6 +111,7 @@ void execute_store_u32_safe(u32 address, u32 source);
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#define reg_x5 ARMREG_R8
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#define mem_reg (~0U)
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#define save1_reg 21
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/*
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@ -1415,7 +1417,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define arm_block_memory_adjust_pc_load() \
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if(reg_list & 0x8000) \
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{ \
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generate_mov(reg_a0, reg_rv); \
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generate_indirect_branch_arm(); \
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} \
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@ -1463,12 +1464,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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arm_block_memory_offset_##offset_type(); \
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arm_block_memory_writeback_##access_type(writeback_type); \
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ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
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generate_store_reg(reg_s0, save1_reg); \
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\
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for(i = 0; i < 16; i++) \
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{ \
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if((reg_list >> i) & 0x01) \
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{ \
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cycle_count++; \
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generate_load_reg(reg_s0, save1_reg); \
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generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
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if(reg_list & ~((2 << i) - 1)) \
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{ \
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@ -1493,12 +1496,12 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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generate_load_reg(reg_a0, rn); \
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generate_function_call(execute_load_##type); \
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write32((pc + 8)); \
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generate_mov(reg_s0, reg_rv); \
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generate_mov(reg_a2, reg_rv); \
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generate_load_reg(reg_a0, rn); \
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generate_load_reg(reg_a1, rm); \
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generate_store_reg(reg_a2, rd); \
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generate_function_call(execute_store_##type); \
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write32((pc + 4)); \
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generate_store_reg(reg_s0, rd); \
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} \
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@ -1729,13 +1732,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define thumb_block_memory_extra_down() \
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#define thumb_block_memory_extra_pop_pc() \
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generate_load_reg(reg_s0, save1_reg); \
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generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
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generate_function_call(execute_load_u32); \
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write32((pc + 4)); \
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generate_mov(reg_a0, reg_rv); \
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generate_indirect_branch_cycle_update(thumb) \
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#define thumb_block_memory_extra_push_lr(base_reg) \
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generate_load_reg(reg_s0, save1_reg); \
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generate_add_reg_reg_imm(reg_a0, reg_s0, (bit_count[reg_list] * 4), 0); \
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generate_load_reg(reg_a1, REG_LR); \
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generate_function_call(execute_store_u32_safe) \
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@ -1782,12 +1786,14 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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ARM_BIC_REG_IMM(0, reg_s0, reg_s0, 0x03, 0); \
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thumb_block_address_preadjust_##pre_op(); \
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thumb_block_address_postadjust_##post_op(base_reg); \
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generate_store_reg(reg_s0, save1_reg); \
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\
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for(i = 0; i < 8; i++) \
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{ \
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if((reg_list >> i) & 0x01) \
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{ \
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cycle_count++; \
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generate_load_reg(reg_s0, save1_reg); \
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generate_add_reg_reg_imm(reg_a0, reg_s0, offset, 0); \
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if(reg_list & ~((2 << i) - 1)) \
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{ \
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@ -45,15 +45,14 @@ _##symbol:
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#define CHANGED_PC_STATUS (31 * 4)
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#define COMPLETED_FRAME (32 * 4)
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#define OAM_UPDATED (33 * 4)
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#define MAIN_THREAD_SP (34 * 4)
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#define reg_a0 r0
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#define reg_a1 r1
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#define reg_a2 r2
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#define reg_s0 r9
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#define reg_base sp
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#define reg_flags r11
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#define reg_base r11
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#define reg_flags r9
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#define reg_cycles r12
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@ -151,11 +150,9 @@ _##symbol:
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@ registers which are important to the dynarec.
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#define call_c_function(function) ;\
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ldr sp, [reg_base, #MAIN_THREAD_SP] ;\
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stmdb sp!, { call_c_saved_regs } ;\
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bl function ;\
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ldmia sp!, { call_c_saved_regs } ;\
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ldr sp, =reg ;\
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@ Jumps to PC (ARM or Thumb modes)
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@ This is really two functions/routines in one
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@ -483,9 +480,7 @@ defsymbl(execute_arm_translate)
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@ save the registers to be able to return later
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stmdb sp!, { r4, r5, r6, r7, r8, r9, r10, r11, r12, lr }
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ldr r1, =reg @ reg to r1
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str sp, [r1, #MAIN_THREAD_SP] @ store the current sp
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ldr sp, =reg @ reg_base = sp (loading addr)
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ldr reg_base, =reg @ init base_reg
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mvn reg_cycles, r0 @ load cycle counter
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@ -515,8 +510,6 @@ defsymbl(execute_arm_translate)
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@ Epilogue to return to the main thread (whatever called execute_arm_translate)
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return_to_main:
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@ restore the stack pointer
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ldr sp, [reg_base, #MAIN_THREAD_SP]
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@ restore the saved regs and return
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ldmia sp!, { r4, r5, r6, r7, r8, r9, r10, r11, r12, lr }
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bx lr
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