(iOS) Compatibility patches pt. 1
This commit is contained in:
twinaphex
parent
89feda2e3e
commit
d6c3c8dee6
109
arm/arm_stub.S
109
arm/arm_stub.S
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@ -1,42 +1,5 @@
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.align 2
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.align 2
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.globl arm_update_gba_arm
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.globl arm_update_gba_thumb
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.globl arm_update_gba_idle_arm
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.globl arm_update_gba_idle_thumb
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.globl arm_indirect_branch_arm
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.globl arm_indirect_branch_thumb
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.globl arm_indirect_branch_dual_arm
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.globl arm_indirect_branch_dual_thumb
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.globl execute_arm_translate
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.globl execute_store_u8
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.globl execute_store_u16
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.globl execute_store_u32
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.globl execute_store_u32_safe
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.globl execute_load_u8
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.globl execute_load_s8
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.globl execute_load_u16
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.globl execute_load_s16
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.globl execute_load_u32
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.globl execute_store_cpsr
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.globl execute_read_spsr
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.globl execute_store_spsr
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.globl execute_spsr_restore
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.globl execute_swi_arm
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.globl execute_swi_thumb
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.globl execute_patch_bios_read
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.globl execute_patch_bios_protect
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.globl execute_bios_ptr_protected
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.globl execute_bios_rom_ptr
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.globl invalidate_icache_region
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.globl invalidate_icache_region
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.globl invalidate_cache_region
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.globl invalidate_cache_region
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@ -213,7 +176,11 @@
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#define arm_update_gba_builder(name, mode, return_op) ;\
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#define arm_update_gba_builder(name, mode, return_op) ;\
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;\
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;\
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.align 2 ;\
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.globl arm_update_gba_##name ;\
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.globl _arm_update_gba_##name ;\
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arm_update_gba_##name: ;\
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arm_update_gba_##name: ;\
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_arm_update_gba_##name: ;\
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load_pc_##return_op() ;\
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load_pc_##return_op() ;\
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str r0, [reg_base, #REG_PC] /* write out the PC */;\
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str r0, [reg_base, #REG_PC] /* write out the PC */;\
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;\
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;\
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@ -265,19 +232,31 @@ arm_update_gba_builder(idle_thumb, thumb, add)
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@ Input:
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@ Input:
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@ r0: PC to branch to
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@ r0: PC to branch to
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.align 2
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.globl arm_indirect_branch_arm
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.globl _arm_indirect_branch_arm
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arm_indirect_branch_arm:
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arm_indirect_branch_arm:
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_arm_indirect_branch_arm:
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save_flags()
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save_flags()
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call_c_function(block_lookup_address_arm)
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call_c_function(block_lookup_address_arm)
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restore_flags()
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restore_flags()
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bx r0
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bx r0
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.align 2
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.globl arm_indirect_branch_thumb
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.globl _arm_indirect_branch_thumb
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arm_indirect_branch_thumb:
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arm_indirect_branch_thumb:
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_arm_indirect_branch_thumb:
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save_flags()
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save_flags()
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call_c_function(block_lookup_address_thumb)
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call_c_function(block_lookup_address_thumb)
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restore_flags()
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restore_flags()
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bx r0
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bx r0
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.align 2
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.globl arm_indirect_branch_dual_arm
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.globl _arm_indirect_branch_dual_arm
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arm_indirect_branch_dual_arm:
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arm_indirect_branch_dual_arm:
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_arm_indirect_branch_dual_arm:
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save_flags()
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save_flags()
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tst r0, #0x01 @ check lower bit
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tst r0, #0x01 @ check lower bit
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bne 1f @ if set going to Thumb mode
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bne 1f @ if set going to Thumb mode
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@ -296,7 +275,11 @@ arm_indirect_branch_dual_arm:
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restore_flags()
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restore_flags()
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bx r0 @ return
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bx r0 @ return
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.align 2
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.globl arm_indirect_branch_dual_thumb
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.globl _arm_indirect_branch_dual_thumb
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arm_indirect_branch_dual_thumb:
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arm_indirect_branch_dual_thumb:
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_arm_indirect_branch_dual_thumb:
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save_flags()
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save_flags()
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tst r0, #0x01 @ check lower bit
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tst r0, #0x01 @ check lower bit
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beq 1f @ if set going to ARM mode
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beq 1f @ if set going to ARM mode
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@ -323,7 +306,11 @@ arm_indirect_branch_dual_thumb:
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@ r1: bitmask of which bits in cpsr to update
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@ r1: bitmask of which bits in cpsr to update
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@ r2: current PC
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@ r2: current PC
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.align 2
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.globl execute_store_cpsr
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.globl _execute_store_cpsr
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execute_store_cpsr:
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execute_store_cpsr:
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_execute_store_cpsr:
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save_flags()
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save_flags()
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and reg_flags, r0, r1 @ reg_flags = new_cpsr & store_mask
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and reg_flags, r0, r1 @ reg_flags = new_cpsr & store_mask
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ldr r0, [reg_base, #REG_CPSR] @ r0 = cpsr
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ldr r0, [reg_base, #REG_CPSR] @ r0 = cpsr
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@ -356,7 +343,11 @@ execute_store_cpsr:
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@ r0: new cpsr value
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@ r0: new cpsr value
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@ r1: bitmask of which bits in spsr to update
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@ r1: bitmask of which bits in spsr to update
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.align 2
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.globl execute_store_spsr
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.globl _execute_store_spsr
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execute_store_spsr:
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execute_store_spsr:
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_execute_store_spsr:
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ldr r1, =spsr @ r1 = spsr
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = CPU_MODE
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ldr r2, [reg_base, #CPU_MODE] @ r2 = CPU_MODE
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str r0, [r1, r2, lsl #2] @ spsr[CPU_MODE] = new_spsr
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str r0, [r1, r2, lsl #2] @ spsr[CPU_MODE] = new_spsr
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@ -367,7 +358,11 @@ execute_store_spsr:
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@ Output:
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@ Output:
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@ r0: spsr
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@ r0: spsr
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.align 2
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.globl execute_read_spsr
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.globl _execute_read_spsr
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execute_read_spsr:
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execute_read_spsr:
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_execute_read_spsr:
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ldr r0, =spsr @ r0 = spsr
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ldr r0, =spsr @ r0 = spsr
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ldr r1, [reg_base, #CPU_MODE] @ r1 = CPU_MODE
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ldr r1, [reg_base, #CPU_MODE] @ r1 = CPU_MODE
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ldr r0, [r0, r1, lsl #2] @ r0 = spsr[CPU_MODE]
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ldr r0, [r0, r1, lsl #2] @ r0 = spsr[CPU_MODE]
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@ -379,7 +374,11 @@ execute_read_spsr:
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@ Input:
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@ Input:
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@ r0: current pc
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@ r0: current pc
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.align 2
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.globl execute_spsr_restore
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.globl _execute_spsr_restore
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execute_spsr_restore:
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execute_spsr_restore:
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_execute_spsr_restore:
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save_flags()
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save_flags()
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ldr r1, =spsr @ r1 = spsr
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ldr r1, =spsr @ r1 = spsr
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ldr r2, [reg_base, #CPU_MODE] @ r2 = cpu_mode
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ldr r2, [reg_base, #CPU_MODE] @ r2 = cpu_mode
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@ -415,7 +414,11 @@ execute_spsr_restore:
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#define execute_swi_builder(mode) ;\
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#define execute_swi_builder(mode) ;\
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;\
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;\
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.align 2 ;\
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.globl execute_swi_##mode ;\
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.globl _execute_swi_##mode ;\
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execute_swi_##mode: ;\
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execute_swi_##mode: ;\
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_execute_swi_##mode: ;\
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save_flags() ;\
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save_flags() ;\
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ldr r1, =reg_mode /* r1 = reg_mode */;\
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ldr r1, =reg_mode /* r1 = reg_mode */;\
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/* reg_mode[MODE_SUPERVISOR][6] = pc */;\
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/* reg_mode[MODE_SUPERVISOR][6] = pc */;\
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@ -448,8 +451,11 @@ execute_swi_builder(thumb)
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#define execute_swi_function_builder(swi_function, mode) ;\
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#define execute_swi_function_builder(swi_function, mode) ;\
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;\
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;\
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.globl execute_swi_hle_##swi_function##_##mode ;\
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.align 2 ;\
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.globl execute_swi_hle_##swi_function##_##mode ;\
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.globl _execute_swi_hle_##swi_function##_##mode ;\
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execute_swi_hle_##swi_function##_##mode: ;\
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execute_swi_hle_##swi_function##_##mode: ;\
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_execute_swi_hle_##swi_function##_##mode: ;\
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save_flags() ;\
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save_flags() ;\
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store_registers_##mode() ;\
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store_registers_##mode() ;\
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call_c_function(execute_swi_hle_##swi_function##_c) ;\
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call_c_function(execute_swi_hle_##swi_function##_c) ;\
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@ -470,7 +476,11 @@ execute_swi_function_builder(div, thumb)
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@ Uses sp as reg_base; must hold consistently true.
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@ Uses sp as reg_base; must hold consistently true.
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.align 2
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.globl execute_arm_translate
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.globl _execute_arm_translate
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execute_arm_translate:
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execute_arm_translate:
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_execute_arm_translate:
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sub sp, sp, #0x100 @ allocate room for register data
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sub sp, sp, #0x100 @ allocate room for register data
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mvn reg_cycles, r0 @ load cycle counter
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mvn reg_cycles, r0 @ load cycle counter
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@ -537,7 +547,11 @@ execute_arm_translate:
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#define execute_store_builder(store_type, store_op, load_op) ;\
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#define execute_store_builder(store_type, store_op, load_op) ;\
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;\
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;\
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.align 2 ;\
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.globl execute_store_u##store_type ;\
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.globl _execute_store_u##store_type ;\
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execute_store_u##store_type: ;\
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execute_store_u##store_type: ;\
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_execute_store_u##store_type: ;\
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execute_store_body(store_type, store_op) ;\
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execute_store_body(store_type, store_op) ;\
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sub r2, r2, #0x8000 /* Pointer to code status data */;\
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sub r2, r2, #0x8000 /* Pointer to code status data */;\
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load_op r0, [r2, r0] /* check code flag */;\
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load_op r0, [r2, r0] /* check code flag */;\
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@ -567,7 +581,10 @@ execute_store_builder(16, strh, ldrh)
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execute_store_builder(32, str, ldr)
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execute_store_builder(32, str, ldr)
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.globl execute_store_u32_safe
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.globl _execute_store_u32_safe
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execute_store_u32_safe:
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execute_store_u32_safe:
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_execute_store_u32_safe:
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execute_store_body(32_safe, str)
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execute_store_body(32_safe, str)
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restore_flags()
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restore_flags()
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ldmia sp!, { pc } @ return
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ldmia sp!, { pc } @ return
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@ -679,7 +696,11 @@ lookup_pc_arm:
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#define execute_load_builder(load_type, load_function, load_op, mask) ;\
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#define execute_load_builder(load_type, load_function, load_op, mask) ;\
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;\
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;\
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.align 2 ;\
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.globl execute_load_##load_type ;\
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.globl _execute_load_##load_type ;\
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execute_load_##load_type: ;\
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execute_load_##load_type: ;\
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_execute_load_##load_type: ;\
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save_flags() ;\
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save_flags() ;\
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tst r0, mask /* make sure address is in range */;\
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tst r0, mask /* make sure address is in range */;\
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bne ext_load_##load_type /* if not do ext load */;\
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bne ext_load_##load_type /* if not do ext load */;\
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@ -720,7 +741,11 @@ execute_##region##_ptr: ;\
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bx lr /* return */;\
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bx lr /* return */;\
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.align 2
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.globl execute_bios_ptr_protected
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.globl _execute_bios_ptr_protected
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execute_bios_ptr_protected:
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execute_bios_ptr_protected:
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_execute_bios_ptr_protected:
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ldr r1, =bios_read_protect @ load bios read ptr
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ldr r1, =bios_read_protect @ load bios read ptr
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and r0, r0, #0x03 @ only want bottom 2 bits
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and r0, r0, #0x03 @ only want bottom 2 bits
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bx lr @ return
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bx lr @ return
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@ -889,7 +914,11 @@ load_ptr_read_function_table:
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@ Patch the read function table to allow for BIOS reads.
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@ Patch the read function table to allow for BIOS reads.
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.align 2
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.globl execute_patch_bios_read
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.globl _execute_patch_bios_read
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execute_patch_bios_read:
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execute_patch_bios_read:
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_execute_patch_bios_read:
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ldr r1, =reg @ r1 = reg
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ldr r1, =reg @ r1 = reg
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ldr r0, =execute_bios_rom_ptr @ r0 = patch function
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ldr r0, =execute_bios_rom_ptr @ r0 = patch function
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ldr r1, [r1]
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ldr r1, [r1]
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@ -899,7 +928,11 @@ execute_patch_bios_read:
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@ Patch the read function table to allow for BIOS reads.
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@ Patch the read function table to allow for BIOS reads.
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.align 2
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.globl execute_patch_bios_protect
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.globl _execute_patch_bios_protect
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execute_patch_bios_protect:
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execute_patch_bios_protect:
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_execute_patch_bios_protect:
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ldr r1, =reg @ r1 = reg
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ldr r1, =reg @ r1 = reg
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ldr r0, =execute_bios_ptr_protected @ r0 = patch function
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ldr r0, =execute_bios_ptr_protected @ r0 = patch function
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ldr r1, [r1]
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ldr r1, [r1]
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@ -1,8 +1,3 @@
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.align 2
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.globl expand_blend
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.globl expand_normal
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@ Input:
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@ Input:
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@ r0 = screen_src_ptr
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@ r0 = screen_src_ptr
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@ r1 = screen_dest_ptr
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@ r1 = screen_dest_ptr
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@ -17,7 +12,11 @@
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.word 0x000003FE @ palette index mask
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.word 0x000003FE @ palette index mask
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.word 0x08010020 @ saturation mask
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.word 0x08010020 @ saturation mask
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.align 2
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.globl expand_blend
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.globl _expand_blend
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expand_blend:
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expand_blend:
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_expand_blend:
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stmdb sp!, { r4, r5, r6, r9, r10, r11, r14 }
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stmdb sp!, { r4, r5, r6, r9, r10, r11, r14 }
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add r0, r0, r2, lsl #2 @ screen_src_ptr += start
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add r0, r0, r2, lsl #2 @ screen_src_ptr += start
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@ -156,7 +155,11 @@ expand_blend:
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.word palette_ram_converted
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.word palette_ram_converted
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.word 0x3FE
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.word 0x3FE
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.align 2
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.globl expand_normal
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.globl _expand_normal
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expand_normal:
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expand_normal:
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_expand_normal:
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stmdb sp!, { r4, r5, r6, r7, r14 }
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stmdb sp!, { r4, r5, r6, r7, r14 }
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add r0, r0, r1, lsl #1 @ screen_ptr += start
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add r0, r0, r1, lsl #1 @ screen_ptr += start
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