lifning/gpsp
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Add ROM mirroring and fix mult. cycle count

Browse source 
This should correct some minor issues in some games.
This commit is contained in:
David Guillen Fandos 2021-05-17 01:14:46 +02:00 • committed by David G. F
parent 2877886ff1
commit aafde6de7b
3 changed files with 19 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
arm/arm_emit.h
View file

@ -1239,12 +1239,10 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define emit_trace_instruction(pc) \ #define emit_trace_instruction(pc) \
generate_save_flags(); \ generate_save_flags(); \
ARM_LDR_IMM(0, ARMREG_SP, reg_base, 34*4); \
ARM_STMDB_WB(0, ARMREG_SP, 0x500C); \ ARM_STMDB_WB(0, ARMREG_SP, 0x500C); \
arm_load_imm_32bit(reg_a0, pc); \ arm_load_imm_32bit(reg_a0, pc); \
generate_function_call(trace_instruction); \ generate_function_call(trace_instruction); \
ARM_LDMIA_WB(0, ARMREG_SP, 0x500C); \ ARM_LDMIA_WB(0, ARMREG_SP, 0x500C); \
arm_load_imm_32bit(ARMREG_SP, (u32)reg); \
generate_restore_flags(); generate_restore_flags();
#define emit_trace_thumb_instruction(pc) \ #define emit_trace_thumb_instruction(pc) \
emit_trace_instruction(pc) emit_trace_instruction(pc)

13
cpu_threaded.c
View file

@ -297,6 +297,7 @@ void translate_icache_sync() {
{ \ { \
/* MUL rd, rm, rs */ \ /* MUL rd, rm, rs */ \
arm_multiply(no, no); \ arm_multiply(no, no); \
cycle_count += 2; /* variable 1..4, pick 2 as an aprox. */ \
} \ } \
} \ } \
else \ else \
@ -314,6 +315,7 @@ void translate_icache_sync() {
case 0: \ case 0: \
/* MULS rd, rm, rs */ \ /* MULS rd, rm, rs */ \
arm_multiply(no, yes); \ arm_multiply(no, yes); \
cycle_count += 2; /* variable 1..4, pick 2 as an aprox. */ \
break; \ break; \
\ \
case 1: \ case 1: \
@ -351,6 +353,7 @@ void translate_icache_sync() {
{ \ { \
/* MLA rd, rm, rs, rn */ \ /* MLA rd, rm, rs, rn */ \
arm_multiply(yes, no); \ arm_multiply(yes, no); \
cycle_count += 3; /* variable 2..5, pick 3 as an aprox. */ \
} \ } \
} \ } \
else \ else \
@ -368,6 +371,7 @@ void translate_icache_sync() {
case 0: \ case 0: \
/* MLAS rd, rm, rs, rn */ \ /* MLAS rd, rm, rs, rn */ \
arm_multiply(yes, yes); \ arm_multiply(yes, yes); \
cycle_count += 3; /* variable 2..5, pick 3 as an aprox. */ \
break; \ break; \
\ \
case 1: \ case 1: \
@ -487,6 +491,7 @@ void translate_icache_sync() {
{ \ { \
/* UMULL rd, rm, rs */ \ /* UMULL rd, rm, rs */ \
arm_multiply_long(u64, no, no); \ arm_multiply_long(u64, no, no); \
cycle_count += 3; /* this is an aproximation :P */ \
} \ } \
} \ } \
else \ else \
@ -504,6 +509,7 @@ void translate_icache_sync() {
case 0: \ case 0: \
/* UMULLS rdlo, rdhi, rm, rs */ \ /* UMULLS rdlo, rdhi, rm, rs */ \
arm_multiply_long(u64, no, yes); \ arm_multiply_long(u64, no, yes); \
cycle_count += 3; /* this is an aproximation :P */ \
break; \ break; \
\ \
case 1: \ case 1: \
@ -541,6 +547,7 @@ void translate_icache_sync() {
{ \ { \
/* UMLAL rd, rm, rs */ \ /* UMLAL rd, rm, rs */ \
arm_multiply_long(u64_add, yes, no); \ arm_multiply_long(u64_add, yes, no); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
} \ } \
} \ } \
else \ else \
@ -558,6 +565,7 @@ void translate_icache_sync() {
case 0: \ case 0: \
/* UMLALS rdlo, rdhi, rm, rs */ \ /* UMLALS rdlo, rdhi, rm, rs */ \
arm_multiply_long(u64_add, yes, yes); \ arm_multiply_long(u64_add, yes, yes); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
break; \ break; \
\ \
case 1: \ case 1: \
@ -595,6 +603,7 @@ void translate_icache_sync() {
{ \ { \
/* SMULL rd, rm, rs */ \ /* SMULL rd, rm, rs */ \
arm_multiply_long(s64, no, no); \ arm_multiply_long(s64, no, no); \
cycle_count += 2; /* Between 1 and 4 cycles? */ \
} \ } \
} \ } \
else \ else \
@ -612,6 +621,7 @@ void translate_icache_sync() {
case 0: \ case 0: \
/* SMULLS rdlo, rdhi, rm, rs */ \ /* SMULLS rdlo, rdhi, rm, rs */ \
arm_multiply_long(s64, no, yes); \ arm_multiply_long(s64, no, yes); \
cycle_count += 2; /* Between 1 and 4 cycles? */ \
break; \ break; \
\ \
case 1: \ case 1: \
@ -649,6 +659,7 @@ void translate_icache_sync() {
{ \ { \
/* SMLAL rd, rm, rs */ \ /* SMLAL rd, rm, rs */ \
arm_multiply_long(s64_add, yes, no); \ arm_multiply_long(s64_add, yes, no); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
} \ } \
} \ } \
else \ else \
@ -666,6 +677,7 @@ void translate_icache_sync() {
case 0: \ case 0: \
/* SMLALS rdlo, rdhi, rm, rs */ \ /* SMLALS rdlo, rdhi, rm, rs */ \
arm_multiply_long(s64_add, yes, yes); \ arm_multiply_long(s64_add, yes, yes); \
cycle_count += 3; /* Between 2 and 5 cycles? */ \
break; \ break; \
\ \
case 1: \ case 1: \
@ -1870,6 +1882,7 @@ void translate_icache_sync() {
case 0x01: \ case 0x01: \
/* MUL rd, rs */ \ /* MUL rd, rs */ \
thumb_data_proc(alu_op, muls, reg, rd, rd, rs); \ thumb_data_proc(alu_op, muls, reg, rd, rd, rs); \
cycle_count += 2; /* Between 1 and 4 extra cycles */ \
break; \ break; \
\ \
case 0x02: \ case 0x02: \

12
gba_memory.c
View file

@ -3155,12 +3155,12 @@ static void init_memory_gamepak(void)
} }
else else
{ {
map_region(read, 0x8000000, 0x8000000 + gamepak_size, 1024, gamepak_rom); /* Map the ROM using mirroring, not many games use it */
map_null(read, 0x8000000 + gamepak_size, 0xA000000); unsigned numblocks = gamepak_size >> 15;
map_region(read, 0xA000000, 0xA000000 + gamepak_size, 1024, gamepak_rom); map_region(read, 0x8000000, 0xA000000, numblocks, gamepak_rom);
map_null(read, 0xA000000 + gamepak_size, 0xC000000); map_region(read, 0xA000000, 0xC000000, numblocks, gamepak_rom);
map_region(read, 0xC000000, 0xC000000 + gamepak_size, 1024, gamepak_rom); map_region(read, 0xC000000, 0xD000000, numblocks, gamepak_rom);
map_null(read, 0xC000000 + gamepak_size, 0xE000000); /* Do not map D-E regions since they are also used for FLASH */
} }
} }