wip, endian loads (but not stores)
This commit is contained in:
parent
086f16f098
commit
a7c745886c
|
@ -2050,6 +2050,30 @@ static void emit_mem_access_loadop(
|
|||
switch (size) {
|
||||
case 2:
|
||||
mips_emit_lw(reg_rv, reg_rv, (base_addr & 0xffff));
|
||||
/*
|
||||
400230: 00042e00 sll a1,a0,0x18
|
||||
400234: 00041602 srl v0,a0,0x18
|
||||
400238: 00041a02 srl v1,a0,0x8
|
||||
40023c: 00451025 or v0,v0,a1
|
||||
400240: 3063ff00 andi v1,v1,0xff00
|
||||
400244: 00431025 or v0,v0,v1
|
||||
400248: 00042200 sll a0,a0,0x8
|
||||
40024c: 3c0300ff lui v1,0xff
|
||||
400250: 00832024 and a0,a0,v1
|
||||
400258: 00441025 or v0,v0,a0
|
||||
*/
|
||||
#ifdef NINTENDO64 // byte order swap
|
||||
mips_emit_sll(reg_temp, reg_rv, 24);
|
||||
mips_emit_srl(mips_reg_k1, reg_rv, 24);
|
||||
mips_emit_srl(mips_reg_k2, reg_rv, 8);
|
||||
mips_emit_or(mips_reg_k1, mips_reg_k1, reg_temp);
|
||||
mips_emit_andi(mips_reg_k2, mips_reg_k2, 0xff00);
|
||||
mips_emit_or(mips_reg_k1, mips_reg_k1, mips_reg_k2);
|
||||
mips_emit_sll(reg_rv, reg_rv, 8);
|
||||
mips_emit_lui(mips_reg_k2, 0xff);
|
||||
mips_emit_and(reg_rv, reg_rv, mips_reg_k2);
|
||||
mips_emit_or(reg_rv, mips_reg_k1, reg_rv);
|
||||
#endif
|
||||
break;
|
||||
case 1:
|
||||
if (signext) {
|
||||
|
@ -2062,6 +2086,27 @@ static void emit_mem_access_loadop(
|
|||
} else {
|
||||
mips_emit_lhu(reg_rv, reg_rv, (base_addr & 0xffff));
|
||||
}
|
||||
/*
|
||||
this first part's signext stuff... maybe not always necessary here?
|
||||
400218: 00021400 sll v0,v0,0x10
|
||||
40021c: 00021403 sra v0,v0,0x10
|
||||
400220: 3042ffff andi v0,v0,0xffff
|
||||
|
||||
400224: 00021a00 sll v1,v0,0x8
|
||||
400228: 00021202 srl v0,v0,0x8
|
||||
40022c: 00621025 or v0,v1,v0
|
||||
400230: 3042ffff andi v0,v0,0xffff
|
||||
*/
|
||||
#ifdef NINTENDO64
|
||||
mips_emit_sll(reg_temp, reg_rv, 8);
|
||||
mips_emit_srl(reg_rv, reg_rv, 8);
|
||||
mips_emit_or(reg_rv, reg_temp, reg_rv);
|
||||
mips_emit_andi(reg_rv, reg_rv, 0xffff);
|
||||
if (signext) {
|
||||
mips_emit_sll(reg_rv, reg_rv, 16);
|
||||
mips_emit_sra(reg_rv, reg_rv, 16);
|
||||
}
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
if (signext) {
|
||||
|
|
Loading…
Reference in New Issue