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Move OAM update flag to a register 

Fix a small bug in MIPS dynarec that affects non -G0 targets
This commit is contained in:
David Guillen Fandos 2021-03-25 21:02:06 +01:00
parent 53cc4a2475
commit a494a3f00e
8 changed files with 23 additions and 27 deletions
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4
arm/arm_stub.S
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@ -43,8 +43,8 @@ _##symbol:
#define CPU_HALT_STATE (30 * 4) #define CPU_HALT_STATE (30 * 4)
#define CHANGED_PC_STATUS (31 * 4) #define CHANGED_PC_STATUS (31 * 4)
#define COMPLETED_FRAME (32 * 4) #define COMPLETED_FRAME (32 * 4)
#define OAM_UPDATED (33 * 4)
#define MAIN_THREAD_SP (33 * 4) #define MAIN_THREAD_SP (34 * 4)
#define reg_a0 r0 #define reg_a0 r0
#define reg_a1 r1 #define reg_a1 r1

4
cpu.h
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@ -85,7 +85,8 @@ typedef enum
CPU_MODE = 29, CPU_MODE = 29,
CPU_HALT_STATE = 30, CPU_HALT_STATE = 30,
CHANGED_PC_STATUS = 31, CHANGED_PC_STATUS = 31,
COMPLETED_FRAME = 32 COMPLETED_FRAME = 32,
OAM_UPDATED = 33
} ext_reg_numbers; } ext_reg_numbers;
typedef enum typedef enum
@ -146,7 +147,6 @@ extern u8 *ram_translation_ptr;
extern u32 idle_loop_target_pc; extern u32 idle_loop_target_pc;
extern u32 iwram_stack_optimize; extern u32 iwram_stack_optimize;
extern u32 direct_map_vram;
extern u32 translation_gate_targets; extern u32 translation_gate_targets;
extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES]; extern u32 translation_gate_target_pc[MAX_TRANSLATION_GATES];

15
gba_memory.c
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@ -342,14 +342,9 @@ gamepak_swap_entry_type *gamepak_memory_map;
// a lot. // a lot.
FILE *gamepak_file_large = NULL; FILE *gamepak_file_large = NULL;
u32 direct_map_vram = 0;
// Writes to these respective locations should trigger an update // Writes to these respective locations should trigger an update
// so the related subsystem may react to it. // so the related subsystem may react to it.
// If OAM is written to:
u32 oam_update = 1;
// If GBC audio is written to: // If GBC audio is written to:
u32 gbc_sound_update = 0; u32 gbc_sound_update = 0;
@ -755,7 +750,7 @@ cpu_alert_type function_cc write_io_register8(u32 address, u32 value)
u32 dispcnt = io_registers[REG_DISPCNT]; u32 dispcnt = io_registers[REG_DISPCNT];
if((value & 0x07) != (dispcnt & 0x07)) if((value & 0x07) != (dispcnt & 0x07))
oam_update = 1; reg[OAM_UPDATED] = 1;
address8(io_registers, 0x00) = value; address8(io_registers, 0x00) = value;
break; break;
@ -1171,7 +1166,7 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
{ {
u32 dispcnt = io_registers[REG_DISPCNT]; u32 dispcnt = io_registers[REG_DISPCNT];
if((value & 0x07) != (dispcnt & 0x07)) if((value & 0x07) != (dispcnt & 0x07))
oam_update = 1; reg[OAM_UPDATED] = 1;
address16(io_registers, 0x00) = value; address16(io_registers, 0x00) = value;
break; break;
@ -1934,7 +1929,7 @@ void function_cc write_rtc(u32 address, u32 value)
\ \
case 0x07: \ case 0x07: \
/* OAM RAM */ \ /* OAM RAM */ \
oam_update = 1; \ reg[OAM_UPDATED] = 1; \
address##type(oam_ram, address & 0x3FF) = value; \ address##type(oam_ram, address & 0x3FF) = value; \
break; \ break; \
\ \
@ -2529,7 +2524,7 @@ dma_region_type dma_region_map[16] =
dma_smc_vars_##type() dma_smc_vars_##type()
#define dma_oam_ram_dest() \ #define dma_oam_ram_dest() \
oam_update = 1 \ reg[OAM_UPDATED] = 1 \
#define dma_vars_oam_ram(type) \ #define dma_vars_oam_ram(type) \
dma_oam_ram_##type() \ dma_oam_ram_##type() \
@ -3331,7 +3326,7 @@ void gba_load_state(const void* src)
wipe_caches(); wipe_caches();
#endif #endif
oam_update = 1; reg[OAM_UPDATED] = 1;
gbc_sound_update = 1; gbc_sound_update = 1;
for(i = 0; i < 512; i++) for(i = 0; i < 512; i++)

2
main.c
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@ -158,7 +158,7 @@ u32 update_gba(void)
if((dispstat & 0x01) == 0) if((dispstat & 0x01) == 0)
{ {
u32 i; u32 i;
if(oam_update) if(reg[OAM_UPDATED])
oam_update_count++; oam_update_count++;
if(no_alpha) if(no_alpha)

8
psp/mips_emit.h
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@ -2512,7 +2512,8 @@ u8 swi_hle_handle[256] =
#define ReOff_SaveR1 (21*4) // 3 save scratch regs #define ReOff_SaveR1 (21*4) // 3 save scratch regs
#define ReOff_SaveR2 (22*4) #define ReOff_SaveR2 (22*4)
#define ReOff_SaveR3 (23*4) #define ReOff_SaveR3 (23*4)
#define ReOff_GP_Save (32*4) // GP_SAVE #define ReOff_OamUpd (33*4) // OAM_UPDATED
#define ReOff_GP_Save (34*4) // GP_SAVE
// Saves all regs to their right slot and loads gp // Saves all regs to their right slot and loads gp
#define emit_save_regs(save_a2) { \ #define emit_save_regs(save_a2) { \
@ -2873,9 +2874,8 @@ static void emit_pmemst_stub(
// Post processing store: // Post processing store:
// Signal that OAM was updated // Signal that OAM was updated
if (region == 7) { if (region == 7) {
u32 palcaddr = (u32)&oam_update; // Write any nonzero data
mips_emit_lui(reg_temp, ((palcaddr + 0x8000) >> 16)); mips_emit_sw(reg_base, reg_base, ReOff_OamUpd);
mips_emit_sw(reg_base, reg_temp, palcaddr & 0xffff); // Write any nonzero data
generate_function_return_swap_delay(); generate_function_return_swap_delay();
} }
else { else {

4
psp/mips_stub.S
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@ -52,6 +52,7 @@
.global reg .global reg
.global spsr .global spsr
.global reg_mode .global reg_mode
.global oam_update
# MIPS register layout: # MIPS register layout:
@ -116,7 +117,8 @@
.equ CPU_HALT_STATE, (30 * 4) .equ CPU_HALT_STATE, (30 * 4)
.equ CHANGED_PC_STATUS, (31 * 4) .equ CHANGED_PC_STATUS, (31 * 4)
.equ COMPLETED_FRAME, (32 * 4) .equ COMPLETED_FRAME, (32 * 4)
.equ GP_SAVE, (33 * 4) .equ OAM_UPDATED, (33 * 4)
.equ GP_SAVE, (34 * 4)
.equ SPSR_BASE, (0x900) .equ SPSR_BASE, (0x900)
.equ REGMODE_BASE, (0x900 + 24) .equ REGMODE_BASE, (0x900 + 24)

4
video.c
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@ -4429,10 +4429,10 @@ void update_scanline(void)
// If OAM has been modified since the last scanline has been updated then // If OAM has been modified since the last scanline has been updated then
// reorder and reprofile the OBJ lists. // reorder and reprofile the OBJ lists.
if(oam_update) if(reg[OAM_UPDATED])
{ {
order_obj(video_mode); order_obj(video_mode);
oam_update = 0; reg[OAM_UPDATED] = 0;
} }
order_layers((dispcnt >> 8) & active_layers[video_mode]); order_layers((dispcnt >> 8) & active_layers[video_mode]);

9
x86/x86_stub.S
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@ -28,7 +28,6 @@ _##symbol:
#ifndef _WIN32 #ifndef _WIN32
# External symbols (data + functions) # External symbols (data + functions)
#define _oam_update oam_update
#define _iwram iwram #define _iwram iwram
#define _ewram ewram #define _ewram ewram
#define _vram vram #define _vram vram
@ -50,7 +49,6 @@ _##symbol:
#define _execute_store_cpsr_body execute_store_cpsr_body #define _execute_store_cpsr_body execute_store_cpsr_body
#endif #endif
.global _oam_update
.global _iwram .global _iwram
.global _ewram .global _ewram
.global _vram .global _vram
@ -75,6 +73,7 @@ _##symbol:
.equ CPU_HALT_STATE, (30 * 4) .equ CPU_HALT_STATE, (30 * 4)
.equ CHANGED_PC_STATUS, (31 * 4) .equ CHANGED_PC_STATUS, (31 * 4)
.equ COMPLETED_FRAME, (32 * 4) .equ COMPLETED_FRAME, (32 * 4)
.equ OAM_UPDATED, (33 * 4)
# destroys ecx and edx # destroys ecx and edx
@ -241,7 +240,7 @@ ext_store_vram8b:
ret ret
ext_store_oam8: ext_store_oam8:
movl $1, _oam_update # flag OAM update movl $1, OAM_UPDATED(%ebx) # flag OAM update
and $0x3FE, %eax # wrap around address and align to 16bits and $0x3FE, %eax # wrap around address and align to 16bits
mov %dl, %dh # copy lower 8bits of value into full 16bits mov %dl, %dh # copy lower 8bits of value into full 16bits
mov %dx, _oam_ram(%eax) # perform 16bit store mov %dx, _oam_ram(%eax) # perform 16bit store
@ -332,7 +331,7 @@ ext_store_vram16b:
ret ret
ext_store_oam16: ext_store_oam16:
movl $1, _oam_update # flag OAM update movl $1, OAM_UPDATED(%ebx) # flag OAM update
and $0x3FF, %eax # wrap around address and $0x3FF, %eax # wrap around address
mov %dx, _oam_ram(%eax) # perform 16bit store mov %dx, _oam_ram(%eax) # perform 16bit store
ret ret
@ -410,7 +409,7 @@ ext_store_vram32b:
ret ret
ext_store_oam32: ext_store_oam32:
movl $1, _oam_update # flag OAM update movl $1, OAM_UPDATED(%ebx) # flag OAM update
and $0x3FF, %eax # wrap around address and $0x3FF, %eax # wrap around address
mov %edx, _oam_ram(%eax) # perform 32bit store mov %edx, _oam_ram(%eax) # perform 32bit store
ret ret