Minor unused stuff cleanup
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c0804fa48d
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@ -1448,12 +1448,6 @@ static void trace_instruction(u32 pc, u32 mode)
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#define word_bit_count(word) \
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(bit_count[word >> 8] + bit_count[word & 0xFF]) \
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#define sprint_no(access_type, pre_op, post_op, wb) \
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#define sprint_yes(access_type, pre_op, post_op, wb) \
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printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
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/* TODO: Make these use cached registers. Implement iwram_stack_optimize. */
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#define arm_block_memory_load() \
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5
cpu.c
5
cpu.c
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@ -1096,11 +1096,6 @@ const u32 psr_masks[16] =
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#define word_bit_count(word) \
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(bit_count[word >> 8] + bit_count[word & 0xFF]) \
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#define sprint_no(access_type, offset_type, writeback_type) \
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#define sprint_yes(access_type, offset_type, writeback_type) \
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printf("sbit on %s %s %s\n", #access_type, #offset_type, #writeback_type) \
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#define arm_block_writeback_load() \
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if(!((reg_list >> rn) & 0x01)) \
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{ \
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@ -1395,11 +1395,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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#define word_bit_count(word) \
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(bit_count[word >> 8] + bit_count[word & 0xFF]) \
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#define sprint_no(access_type, pre_op, post_op, wb) \
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#define sprint_yes(access_type, pre_op, post_op, wb) \
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printf("sbit on %s %s %s %s\n", #access_type, #pre_op, #post_op, #wb) \
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#define arm_block_memory_load() \
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generate_function_call_swap_delay(execute_aligned_load32); \
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generate_store_reg(reg_rv, i) \
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@ -1529,44 +1524,6 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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} \
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} \
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#define arm_block_writeback_no()
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#define arm_block_writeback_yes() \
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mips_emit_addu(arm_to_mips_reg[rn], reg_a2, reg_zero) \
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#define arm_block_address_preadjust_up_full(wb) \
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mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \
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((word_bit_count(reg_list)) * 4)); \
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arm_block_writeback_##wb() \
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#define arm_block_address_preadjust_up(wb) \
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mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], 4); \
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arm_block_writeback_##wb() \
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#define arm_block_address_preadjust_down_full(wb) \
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mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \
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-((word_bit_count(reg_list)) * 4)); \
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arm_block_writeback_##wb() \
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#define arm_block_address_preadjust_down(wb) \
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mips_emit_addiu(reg_a2, arm_to_mips_reg[rn], \
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-(((word_bit_count(reg_list)) * 4) - 4)); \
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arm_block_writeback_##wb()
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#define arm_block_address_preadjust_no(wb) \
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mips_emit_addu(reg_a2, arm_to_mips_reg[rn], reg_zero) \
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#define arm_block_address_postadjust_no() \
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#define arm_block_address_postadjust_up() \
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mips_emit_addiu(arm_to_mips_reg[rn], reg_a2, \
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((word_bit_count(reg_list)) * 4)) \
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#define arm_block_address_postadjust_down() \
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mips_emit_addiu(arm_to_mips_reg[rn], reg_a2, \
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-((word_bit_count(reg_list)) * 4)) \
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// ARM: rn *must* be different from rm and rd. rm *can* be the same as rd.
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#define arm_swap(type) \
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