[Interp] Simplify PC calculation
This commit is contained in:
David Guillen Fandos
parent
64d0a066b4
commit
875c192257
139
cpu.cc
139
cpu.cc
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@ -566,7 +566,7 @@ const u8 bit_count[256] =
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(v_flag << 28) | (reg[REG_CPSR] & 0xFF) \
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#define check_pc_region() \
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new_pc_region = (pc >> 15); \
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new_pc_region = (reg[REG_PC] >> 15); \
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if(new_pc_region != pc_region) \
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{ \
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pc_region = new_pc_region; \
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@ -578,20 +578,8 @@ const u8 bit_count[256] =
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} \
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#define arm_update_pc() \
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pc = reg[REG_PC] \
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#define arm_pc_offset(val) \
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pc += val; \
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reg[REG_PC] = pc \
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#define arm_pc_offset_update(val) \
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pc += val; \
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reg[REG_PC] = pc \
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#define arm_pc_offset_update_direct(val) \
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pc = val; \
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reg[REG_PC] = pc \
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reg[REG_PC] += val \
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// It should be okay to still generate result flags, spsr will overwrite them.
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@ -606,7 +594,6 @@ const u8 bit_count[256] =
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REG_SPSR(MODE_IRQ) = reg[REG_CPSR]; \
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reg[REG_CPSR] = 0xD2; \
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reg[REG_PC] = 0x00000018; \
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arm_update_pc(); \
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set_cpu_mode(MODE_IRQ); \
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goto arm_loop; \
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} \
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@ -621,7 +608,6 @@ const u8 bit_count[256] =
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set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0xF]); \
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check_for_interrupts(); \
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} \
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arm_update_pc(); \
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\
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if(reg[REG_CPSR] & 0x20) \
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goto thumb_loop; \
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@ -651,11 +637,6 @@ const u8 bit_count[256] =
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dest = expr; \
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arm_pc_offset(-4); \
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reg[rd] = dest; \
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\
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if(rd == 15) \
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{ \
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arm_update_pc(); \
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} \
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} \
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#define flags_vars(src_a, src_b) \
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@ -854,7 +835,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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} \
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\
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if ( \
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(((_address >> 24) == 0) && (pc >= 0x4000)) || /* BIOS reading */ \
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(((_address >> 24) == 0) && (reg[REG_PC] >= 0x4000)) || /* BIOS read */ \
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(_address & aligned_address_mask##size) || /* Unaligned access */ \
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!(map = memory_map_read[_address >> 15]) /* Unmapped memory */ \
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) \
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@ -953,11 +934,6 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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if(rd == 15) \
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reg_op += 4 \
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#define arm_access_memory_pc_postadjust_load() \
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arm_update_pc() \
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#define arm_access_memory_pc_postadjust_store() \
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#define load_reg_op reg[rd] \
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#define store_reg_op reg_op \
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@ -973,7 +949,6 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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arm_pc_offset(-4); \
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arm_access_memory_writeback_##wb(wb_off_op); \
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access_type##_memory_##mem_type(address, access_type##_reg_op); \
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arm_access_memory_pc_postadjust_##access_type(); \
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} \
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#define word_bit_count(word) \
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@ -1020,11 +995,10 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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#define arm_block_memory_writeback_no() \
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#define arm_block_memory_load_pc() \
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load_aligned32(address, pc); \
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reg[REG_PC] = pc \
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load_aligned32(address, reg[REG_PC]); \
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#define arm_block_memory_store_pc() \
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store_aligned32(address, pc + 4) \
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store_aligned32(address, reg[REG_PC] + 4) \
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#define arm_block_memory(access_type, offset_type, writeback_type, s_bit) \
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{ \
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@ -1067,20 +1041,8 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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goto skip_instruction; \
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} \
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#define thumb_update_pc() \
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pc = reg[REG_PC] \
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#define thumb_pc_offset(val) \
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pc += val; \
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reg[REG_PC] = pc \
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#define thumb_pc_offset_update(val) \
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pc += val; \
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reg[REG_PC] = pc \
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#define thumb_pc_offset_update_direct(val) \
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pc = val; \
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reg[REG_PC] = pc \
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reg[REG_PC] += val \
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// Types: add_sub, add_sub_imm, alu_op, imm
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// Affects N/Z/C/V flags
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@ -1298,7 +1260,6 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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if(rd == 15) \
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{ \
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reg[REG_PC] = dest & ~0x01; \
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thumb_update_pc(); \
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} \
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else \
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{ \
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@ -1336,9 +1297,8 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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address -= offset \
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#define thumb_block_address_postadjust_pop_pc() \
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load_memory_u32(address + offset, pc); \
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pc &= ~0x01; \
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reg[REG_PC] = pc; \
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load_memory_u32(address + offset, reg[REG_PC]); \
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reg[REG_PC] &= ~0x01; \
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address += offset + 4 \
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#define thumb_block_address_postadjust_push_lr() \
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@ -1388,7 +1348,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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{ \
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thumb_pc_offset(2); \
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} \
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cycles_remaining -= ws_cyc_nseq[pc >> 24][0]; \
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cycles_remaining -= ws_cyc_nseq[reg[REG_PC] >> 24][0]; \
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} \
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// When a mode change occurs from non-FIQ to non-FIQ retire the current
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@ -1511,21 +1471,16 @@ u16 io_registers[512];
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void execute_arm(u32 cycles)
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{
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u32 pc = reg[REG_PC];
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u32 opcode;
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u32 condition;
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u32 n_flag, z_flag, c_flag, v_flag;
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u32 pc_region = (pc >> 15);
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u32 pc_region = (reg[REG_PC] >> 15);
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u8 *pc_address_block = memory_map_read[pc_region];
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u32 new_pc_region;
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s32 cycles_remaining;
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u32 update_ret;
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cpu_alert_type cpu_alert;
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u32 old_pc;
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(void)old_pc;
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if(!pc_address_block)
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pc_address_block = load_gamepak_page(pc_region & 0x3FF);
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touch_gamepak_page(pc_region);
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@ -1543,7 +1498,6 @@ void execute_arm(u32 cycles)
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}
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cpu_alert = CPU_ALERT_NONE;
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pc = reg[REG_PC];
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extract_flags();
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if(reg[REG_CPSR] & 0x20)
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@ -1556,16 +1510,14 @@ arm_loop:
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collapse_flags();
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/* Process cheats if we are about to execute the cheat hook */
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if (pc == cheat_master_hook)
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if (reg[REG_PC] == cheat_master_hook)
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process_cheats();
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old_pc = pc;
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/* Execute ARM instruction */
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using_instruction(arm);
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check_pc_region();
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pc &= ~0x03;
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opcode = readaddress32(pc_address_block, (pc & 0x7FFF));
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reg[REG_PC] &= ~0x03;
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opcode = readaddress32(pc_address_block, (reg[REG_PC] & 0x7FFF));
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condition = opcode >> 28;
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switch(condition)
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@ -2136,16 +2088,15 @@ arm_loop:
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u32 src = reg[rn];
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if(src & 0x01)
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{
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src -= 1;
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arm_pc_offset_update_direct(src);
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reg[REG_PC] = src - 1;
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reg[REG_CPSR] |= 0x20;
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goto thumb_loop;
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}
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else
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{
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arm_pc_offset_update_direct(src);
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reg[REG_PC] = src;
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}
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cycles_remaining -= ws_cyc_nseq[pc >> 24][1];
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cycles_remaining -= ws_cyc_nseq[reg[REG_PC] >> 24][1];
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}
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else
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{
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@ -3073,8 +3024,8 @@ arm_loop:
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{
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/* B offset */
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arm_decode_branch();
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arm_pc_offset_update(offset + 8);
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cycles_remaining -= ws_cyc_nseq[pc >> 24][1];
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reg[REG_PC] += offset + 8;
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cycles_remaining -= ws_cyc_nseq[reg[REG_PC] >> 24][1];
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break;
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}
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@ -3082,9 +3033,9 @@ arm_loop:
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{
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/* BL offset */
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arm_decode_branch();
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reg[REG_LR] = pc + 4;
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arm_pc_offset_update(offset + 8);
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cycles_remaining -= ws_cyc_nseq[pc >> 24][1];
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reg[REG_LR] = reg[REG_PC] + 4;
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reg[REG_PC] += offset + 8;
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cycles_remaining -= ws_cyc_nseq[reg[REG_PC] >> 24][1];
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break;
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}
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@ -3105,11 +3056,10 @@ arm_loop:
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default:
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// After SWI, we read bios[0xE4]
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reg[REG_BUS_VALUE] = 0xe3a02004;
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REG_MODE(MODE_SUPERVISOR)[6] = pc + 4;
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REG_MODE(MODE_SUPERVISOR)[6] = reg[REG_PC] + 4;
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collapse_flags();
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REG_SPSR(MODE_SUPERVISOR) = reg[REG_CPSR];
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reg[REG_PC] = 0x00000008;
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arm_update_pc();
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// Move to ARM mode, Supervisor mode and disable IRQs
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reg[REG_CPSR] = (reg[REG_CPSR] & ~0x3F) | 0x13 | 0x80;
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set_cpu_mode(MODE_SUPERVISOR);
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@ -3122,9 +3072,9 @@ arm_loop:
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skip_instruction:
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/* End of Execute ARM instruction */
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cycles_remaining -= ws_cyc_seq[(pc >> 24) & 0xF][1];
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cycles_remaining -= ws_cyc_seq[(reg[REG_PC] >> 24) & 0xF][1];
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if (pc == idle_loop_target_pc && cycles_remaining > 0) cycles_remaining = 0;
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if (reg[REG_PC] == idle_loop_target_pc && cycles_remaining > 0) cycles_remaining = 0;
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if (cpu_alert & (CPU_ALERT_HALT | CPU_ALERT_IRQ))
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goto alert;
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@ -3145,17 +3095,15 @@ thumb_loop:
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collapse_flags();
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/* Process cheats if we are about to execute the cheat hook */
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if (pc == cheat_master_hook)
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if (reg[REG_PC] == cheat_master_hook)
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process_cheats();
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old_pc = pc;
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/* Execute THUMB instruction */
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using_instruction(thumb);
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check_pc_region();
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pc &= ~0x01;
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opcode = readaddress16(pc_address_block, (pc & 0x7FFF));
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reg[REG_PC] &= ~0x01;
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opcode = readaddress16(pc_address_block, (reg[REG_PC] & 0x7FFF));
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#ifdef TRACE_INSTRUCTIONS
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interp_trace_instruction(pc, 0);
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@ -3354,13 +3302,12 @@ thumb_loop:
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src = reg[rs];
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if(src & 0x01)
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{
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src -= 1;
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thumb_pc_offset_update_direct(src);
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reg[REG_PC] = src - 1;
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}
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else
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{
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/* Switch to ARM mode */
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thumb_pc_offset_update_direct(src);
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reg[REG_PC] = src;
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reg[REG_CPSR] &= ~0x20;
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collapse_flags();
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goto arm_loop;
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@ -3370,7 +3317,7 @@ thumb_loop:
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case 0x48 ... 0x4F:
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/* LDR r0..7, [pc + imm] */
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thumb_access_memory(load, imm, ((pc-2) & ~2) + (imm * 4) + 4, reg[(opcode >> 8) & 7], u32);
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thumb_access_memory(load, imm, ((reg[REG_PC] - 2) & ~2) + (imm * 4) + 4, reg[(opcode >> 8) & 7], u32);
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break;
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case 0x50:
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@ -3463,7 +3410,7 @@ thumb_loop:
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case 0xA0 ... 0xA7:
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/* ADD r0..7, pc, +imm */
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thumb_add_noflags(imm, ((opcode >> 8) & 7), (pc & ~2) + 4, (imm * 4));
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thumb_add_noflags(imm, ((opcode >> 8) & 7), (reg[REG_PC] & ~2) + 4, (imm * 4));
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break;
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case 0xA8 ... 0xAF:
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@ -3597,10 +3544,9 @@ thumb_loop:
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default:
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// After SWI, we read bios[0xE4]
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reg[REG_BUS_VALUE] = 0xe3a02004;
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REG_MODE(MODE_SUPERVISOR)[6] = pc + 2;
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REG_MODE(MODE_SUPERVISOR)[6] = reg[REG_PC] + 2;
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REG_SPSR(MODE_SUPERVISOR) = reg[REG_CPSR];
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reg[REG_PC] = 0x00000008;
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thumb_update_pc();
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// Move to ARM mode, Supervisor mode and disable IRQs
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reg[REG_CPSR] = (reg[REG_CPSR] & ~0x3F) | 0x13 | 0x80;
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set_cpu_mode(MODE_SUPERVISOR);
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@ -3614,8 +3560,9 @@ thumb_loop:
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{
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/* B label */
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thumb_decode_branch();
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thumb_pc_offset_update(((s32)(offset << 21) >> 20) + 4);
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cycles_remaining -= ws_cyc_nseq[pc >> 24][0];
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s32 br_offset = ((s32)(offset << 21) >> 20) + 4;
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reg[REG_PC] += br_offset;
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cycles_remaining -= ws_cyc_nseq[reg[REG_PC] >> 24][0];
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break;
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}
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@ -3623,7 +3570,7 @@ thumb_loop:
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{
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/* (low word) BL label */
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thumb_decode_branch();
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reg[REG_LR] = pc + 4 + ((s32)(offset << 21) >> 9);
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reg[REG_LR] = reg[REG_PC] + 4 + ((s32)(offset << 21) >> 9);
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thumb_pc_offset(2);
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break;
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}
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@ -3632,19 +3579,19 @@ thumb_loop:
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{
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/* (high word) BL label */
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thumb_decode_branch();
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u32 lr = (pc + 2) | 0x01;
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pc = reg[REG_LR] + (offset * 2);
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reg[REG_LR] = lr;
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reg[REG_PC] = pc;
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cycles_remaining -= ws_cyc_nseq[pc >> 24][0];
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u32 newlr = (reg[REG_PC] + 2) | 0x01;
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u32 newpc = reg[REG_LR] + (offset * 2);
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reg[REG_LR] = newlr;
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reg[REG_PC] = newpc;
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cycles_remaining -= ws_cyc_nseq[newpc >> 24][0];
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break;
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}
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}
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/* End of Execute THUMB instruction */
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cycles_remaining -= ws_cyc_seq[(pc >> 24) & 0xF][0];
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cycles_remaining -= ws_cyc_seq[(reg[REG_PC] >> 24) & 0xF][0];
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if (pc == idle_loop_target_pc && cycles_remaining > 0) cycles_remaining = 0;
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if (reg[REG_PC] == idle_loop_target_pc && cycles_remaining > 0) cycles_remaining = 0;
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if (cpu_alert & (CPU_ALERT_HALT | CPU_ALERT_IRQ))
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goto alert;
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