[interp] Improve interpreter timings and honor WAITCNT
This fixes a few games and makes the interpreter faster (since it doesn't run an overclocked CPU anymore).
This commit is contained in:
David Guillen Fandos
parent
c9c88f3560
commit
84c347edad
16
cpu.c
16
cpu.c
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@ -865,6 +865,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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{ \
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/* Account for cycles and other stats */ \
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u8 region = _address >> 24; \
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cycles_remaining -= ws_cyc_nseq[region][(size - 8) / 16]; \
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memory_region_access_read_##type[region]++; \
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memory_reads_##type++; \
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} \
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@ -890,6 +891,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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if(_address < 0x10000000) \
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{ \
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u8 region = _address >> 24; \
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cycles_remaining -= ws_cyc_nseq[region][(size - 8) / 16]; \
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memory_region_access_write_##type[region]++; \
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memory_writes_##type++; \
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} \
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@ -905,6 +907,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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{ \
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/* Account for cycles and other stats */ \
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u8 region = _address >> 24; \
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cycles_remaining -= ws_cyc_seq[region][1]; \
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memory_region_access_read_u32[region]++; \
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memory_reads_u32++; \
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} \
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@ -925,6 +928,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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{ \
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/* Account for cycles and other stats */ \
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u8 region = _address >> 24; \
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cycles_remaining -= ws_cyc_seq[region][1]; \
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memory_region_access_write_u32[region]++; \
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memory_writes_u32++; \
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} \
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@ -1404,6 +1408,7 @@ const u32 spsr_masks[4] = { 0x00000000, 0x000000EF, 0xF0000000, 0xF00000EF };
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{ \
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thumb_pc_offset(2); \
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} \
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cycles_remaining -= ws_cyc_nseq[pc >> 24][0]; \
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} \
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// When a mode change occurs from non-FIQ to non-FIQ retire the current
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@ -1530,7 +1535,6 @@ void execute_arm(u32 cycles)
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u8 *pc_address_block = memory_map_read[pc_region];
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u32 new_pc_region;
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s32 cycles_remaining;
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u32 cycles_per_instruction = global_cycles_per_instruction;
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cpu_alert_type cpu_alert;
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u32 old_pc;
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@ -1564,7 +1568,6 @@ void execute_arm(u32 cycles)
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arm_loop:
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collapse_flags();
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cycles_per_instruction = global_cycles_per_instruction;
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/* Process cheats if we are about to execute the cheat hook */
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if (pc == cheat_master_hook)
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@ -2156,6 +2159,7 @@ arm_loop:
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{
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arm_pc_offset_update_direct(src);
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}
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cycles_remaining -= ws_cyc_nseq[pc >> 24][1];
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}
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else
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{
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@ -3084,6 +3088,7 @@ arm_loop:
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/* B offset */
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arm_decode_branch();
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arm_pc_offset_update(offset + 8);
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cycles_remaining -= ws_cyc_nseq[pc >> 24][1];
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break;
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}
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@ -3093,6 +3098,7 @@ arm_loop:
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arm_decode_branch();
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reg[REG_LR] = pc + 4;
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arm_pc_offset_update(offset + 8);
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cycles_remaining -= ws_cyc_nseq[pc >> 24][1];
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break;
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}
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@ -3130,7 +3136,7 @@ arm_loop:
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skip_instruction:
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/* End of Execute ARM instruction */
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cycles_remaining -= cycles_per_instruction;
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cycles_remaining -= ws_cyc_seq[(pc >> 24) & 0xF][1];
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if (pc == idle_loop_target_pc && cycles_remaining > 0) cycles_remaining = 0;
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@ -3622,6 +3628,7 @@ thumb_loop:
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/* B label */
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thumb_decode_branch();
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thumb_pc_offset_update(((s32)(offset << 21) >> 20) + 4);
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cycles_remaining -= ws_cyc_nseq[pc >> 24][0];
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break;
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}
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@ -3642,12 +3649,13 @@ thumb_loop:
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pc = reg[REG_LR] + (offset * 2);
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reg[REG_LR] = lr;
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reg[REG_PC] = pc;
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cycles_remaining -= ws_cyc_nseq[pc >> 24][0];
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break;
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}
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}
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/* End of Execute THUMB instruction */
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cycles_remaining -= cycles_per_instruction;
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cycles_remaining -= ws_cyc_seq[(pc >> 24) & 0xF][0];
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if (pc == idle_loop_target_pc && cycles_remaining > 0) cycles_remaining = 0;
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@ -2774,7 +2774,7 @@ u8 function_cc *block_lookup_address_thumb(u32 pc)
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#define arm_instruction_width 4
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#define arm_base_cycles() \
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cycle_count += waitstate_cycles_sequential[pc >> 24][2] \
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cycle_count += def_seq_cycles[pc >> 24][1] \
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// For now this just sets a variable that says flags should always be
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// computed.
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@ -2843,7 +2843,7 @@ u8 function_cc *block_lookup_address_thumb(u32 pc)
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#define thumb_instruction_width 2
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#define thumb_base_cycles() \
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cycle_count += waitstate_cycles_sequential[pc >> 24][1] \
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cycle_count += def_seq_cycles[pc >> 24][0] \
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// Here's how this works: each instruction has three different sets of flag
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// attributes, each consisiting of a 4bit mask describing how that instruction
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127
gba_memory.c
127
gba_memory.c
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@ -269,42 +269,71 @@ static void trigger_timer(u32 timer_number, u32 value)
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write_ioreg(REG_TMXCNT(timer_number), value);
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}
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// This table is configured for sequential access on system defaults
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/* Memory timings */
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const u8 ws012_nonseq[] = {4, 3, 2, 8};
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const u8 ws0_seq[] = {2, 1};
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const u8 ws1_seq[] = {4, 1};
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const u8 ws2_seq[] = {8, 1};
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const u32 waitstate_cycles_sequential[16][3] =
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/* Divided by region and bus width (16/32) */
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u8 ws_cyc_seq[16][2] =
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{
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{ 1, 1, 1 }, // BIOS
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{ 1, 1, 1 }, // Invalid
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{ 3, 3, 6 }, // EWRAM (default settings)
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{ 1, 1, 1 }, // IWRAM
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{ 1, 1, 1 }, // IO Registers
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{ 1, 1, 2 }, // Palette RAM
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{ 1, 1, 2 }, // VRAM
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{ 1, 1, 2 }, // OAM
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{ 3, 3, 6 }, // Gamepak (wait 0)
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{ 3, 3, 6 }, // Gamepak (wait 0)
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{ 5, 5, 9 }, // Gamepak (wait 1)
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{ 5, 5, 9 }, // Gamepak (wait 1)
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{ 9, 9, 17 }, // Gamepak (wait 2)
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{ 9, 9, 17 }, // Gamepak (wait 2)
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{ 1, 1 }, // BIOS
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{ 1, 1 }, // Invalid
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{ 3, 6 }, // EWRAM (default settings)
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{ 1, 1 }, // IWRAM
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{ 1, 1 }, // IO Registers
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{ 1, 2 }, // Palette RAM
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{ 1, 2 }, // VRAM
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{ 1, 2 }, // OAM
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{ 0, 0 }, // Gamepak (wait 0)
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{ 0, 0 }, // Gamepak (wait 0)
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{ 0, 0 }, // Gamepak (wait 1)
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{ 0, 0 }, // Gamepak (wait 1)
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{ 0, 0 }, // Gamepak (wait 2)
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{ 0, 0 }, // Gamepak (wait 2)
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{ 1, 1 }, // Invalid
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{ 1, 1 }, // Invalid
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};
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u8 ws_cyc_nseq[16][2] =
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{
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{ 1, 1 }, // BIOS
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{ 1, 1 }, // Invalid
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{ 3, 6 }, // EWRAM (default settings)
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{ 1, 1 }, // IWRAM
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{ 1, 1 }, // IO Registers
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{ 1, 2 }, // Palette RAM
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{ 1, 2 }, // VRAM
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{ 1, 2 }, // OAM
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{ 0, 0 }, // Gamepak (wait 0)
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{ 0, 0 }, // Gamepak (wait 0)
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{ 0, 0 }, // Gamepak (wait 1)
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{ 0, 0 }, // Gamepak (wait 1)
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{ 0, 0 }, // Gamepak (wait 2)
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{ 0, 0 }, // Gamepak (wait 2)
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{ 1, 1 }, // Invalid
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{ 1, 1 }, // Invalid
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};
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// Different settings for gamepak ws0-2 sequential (2nd) access
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const u32 gamepak_waitstate_sequential[2][3][3] =
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const u32 def_seq_cycles[16][2] =
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{
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{
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{ 3, 3, 6 },
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{ 5, 5, 9 },
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{ 9, 9, 17 }
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},
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{
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{ 2, 2, 3 },
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{ 2, 2, 3 },
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{ 2, 2, 3 }
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}
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{ 1, 1 }, // BIOS
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{ 1, 1 }, // Invalid
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{ 3, 6 }, // EWRAM (default settings)
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{ 1, 1 }, // IWRAM
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{ 1, 1 }, // IO Registers
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{ 1, 2 }, // Palette RAM
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{ 1, 2 }, // VRAM
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{ 1, 2 }, // OAM
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{ 3, 6 }, // Gamepak (wait 0)
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{ 3, 6 }, // Gamepak (wait 0)
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{ 5, 9 }, // Gamepak (wait 1)
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{ 5, 9 }, // Gamepak (wait 1)
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{ 9, 17 }, // Gamepak (wait 2)
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{ 9, 17 }, // Gamepak (wait 2)
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};
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u8 bios_rom[1024 * 16];
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// Up to 128kb, store SRAM, flash ROM, or EEPROM here.
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@ -364,6 +393,34 @@ u32 flash_bank_cnt;
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u32 flash_device_id = FLASH_DEVICE_MACRONIX_64KB;
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void reload_timing_info()
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{
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int i;
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uint16_t waitcnt = read_ioreg(REG_WAITCNT);
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/* Sequential 16 and 32 bit accesses to ROM */
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ws_cyc_seq[0x8][0] = ws_cyc_seq[0x9][0] = 1 + ws0_seq[(waitcnt >> 4) & 1];
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ws_cyc_seq[0xA][0] = ws_cyc_seq[0xB][0] = 1 + ws1_seq[(waitcnt >> 7) & 1];
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ws_cyc_seq[0xC][0] = ws_cyc_seq[0xD][0] = 1 + ws2_seq[(waitcnt >> 10) & 1];
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for (i = 0x8; i <= 0xD; i++)
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{
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/* 32 bit accesses just cost double due to 16 bit bus */
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ws_cyc_seq[i][1] = ws_cyc_seq[i][0] * 2;
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}
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/* Sequential 16 and 32 bit accesses to ROM */
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ws_cyc_nseq[0x8][0] = ws_cyc_nseq[0x9][0] = 1 + ws012_nonseq[(waitcnt >> 2) & 3];
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ws_cyc_nseq[0xA][0] = ws_cyc_nseq[0xB][0] = 1 + ws012_nonseq[(waitcnt >> 5) & 3];
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ws_cyc_nseq[0xC][0] = ws_cyc_nseq[0xD][0] = 1 + ws012_nonseq[(waitcnt >> 8) & 3];
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for (i = 0x8; i <= 0xD; i++)
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{
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/* 32 bit accesses are a non-seq (16) + seq access (16) */
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ws_cyc_nseq[i][1] = 1 + ws_cyc_nseq[i][0] + ws_cyc_seq[i][0];
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}
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}
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u8 read_backup(u32 address)
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{
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u8 value = 0;
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@ -866,8 +923,12 @@ cpu_alert_type function_cc write_io_register16(u32 address, u32 value)
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case REG_VCOUNT:
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break; // Do nothing
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// Registers without side effects
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case REG_WAITCNT:
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write_ioreg(REG_WAITCNT, value);
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reload_timing_info();
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break;
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// Registers without side effects
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default:
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write_ioreg(ioreg, value);
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break;
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@ -2251,8 +2312,8 @@ cpu_alert_type dma_transfer(unsigned dma_chan, int *usedcycles)
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// This is an approximation for the most common case (no region cross)
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if (usedcycles)
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*usedcycles += dmach->length * (
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waitstate_cycles_sequential[src_ptr >> 24][tfsizes] +
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waitstate_cycles_sequential[dst_ptr >> 24][tfsizes]);
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def_seq_cycles[src_ptr >> 24][tfsizes - 1] +
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def_seq_cycles[dst_ptr >> 24][tfsizes - 1]);
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return ret;
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}
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@ -2415,6 +2476,8 @@ void init_memory(void)
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write_ioreg(REG_BG3PD, 0x100);
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write_ioreg(REG_RCNT, 0x8000);
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reload_timing_info();
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backup_type = BACKUP_NONE;
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sram_bankcount = SRAM_SIZE_32KB;
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@ -200,7 +200,10 @@ void function_cc write_backup(u32 address, u32 value);
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void function_cc write_rtc(u32 address, u32 value);
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/* EDIT: Shouldn't this be extern ?! */
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extern const u32 waitstate_cycles_sequential[16][3];
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extern const u32 def_seq_cycles[16][2];
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/* Cycles can change depending on WAITCNT */
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extern u8 ws_cyc_seq[16][2];
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extern u8 ws_cyc_nseq[16][2];
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extern u32 gamepak_size;
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extern char gamepak_title[13];
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2
main.c
2
main.c
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@ -22,8 +22,6 @@
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timer_type timer[4];
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const u32 global_cycles_per_instruction = 1;
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u32 cpu_ticks = 0;
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u32 execute_cycles = 960;
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