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Fix PC calculation for open bus loads 

It was pretty much broken in all platforms, just "ok" enough for it to
work on some games though.
This commit is contained in:
David Guillen Fandos 2021-12-20 19:31:33 +01:00
parent 12cd4e0c06
commit 7b181cb6ff
4 changed files with 12 additions and 12 deletions
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4
arm/arm64_emit.h
View File

@ -1269,7 +1269,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define arm_access_memory_load(mem_type) \
cycle_count += 2; \
generate_load_pc(reg_a1, (pc + 8)); \
generate_load_pc(reg_a1, (pc)); \
generate_function_call(execute_load_##mem_type); \
generate_store_reg(reg_res, rd); \
check_store_reg_pc_no_flags(rd) \
@ -1595,7 +1595,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
#define thumb_access_memory_load(mem_type, reg_rd) \
cycle_count += 2; \
generate_load_pc(reg_a1, (pc + 4)); \
generate_load_pc(reg_a1, (pc)); \
generate_function_call(execute_load_##mem_type); \
generate_store_reg(reg_res, reg_rd) \

4
arm/arm_emit.h
View File

@ -1360,7 +1360,7 @@ static void trace_instruction(u32 pc, u32 mode)
#define arm_access_memory_load(mem_type) \
cycle_count += 2; \
generate_load_call_##mem_type(); \
write32((pc + 8)); \
write32(pc); \
arm_generate_store_reg_pc_no_flags(reg_rv, rd) \
#define arm_access_memory_store(mem_type) \
@ -1732,7 +1732,7 @@ static void trace_instruction(u32 pc, u32 mode)
#define thumb_access_memory_load(mem_type, _rd) \
cycle_count += 2; \
generate_load_call_##mem_type(); \
write32((pc + 4)); \
write32(pc); \
thumb_generate_store_reg(reg_rv, _rd) \
#define thumb_access_memory_store(mem_type, _rd) \

12
gba_memory.c
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@ -504,22 +504,22 @@ void function_cc write_eeprom(u32 unused_address, u32 value)
#define read_open8() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory8(reg[REG_PC] + 4 + (address & 0x03)); \
value = read_memory8(reg[REG_PC] + 8 + (address & 0x03)); \
else \
value = read_memory8(reg[REG_PC] + 2 + (address & 0x01)) \
value = read_memory8(reg[REG_PC] + 4 + (address & 0x01)) \
#define read_open16() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory16(reg[REG_PC] + 4 + (address & 0x02)); \
value = read_memory16(reg[REG_PC] + 8 + (address & 0x02)); \
else \
value = read_memory16(reg[REG_PC] + 2) \
value = read_memory16(reg[REG_PC] + 4) \
#define read_open32() \
if(!(reg[REG_CPSR] & 0x20)) \
value = read_memory32(reg[REG_PC] + 4); \
value = read_memory32(reg[REG_PC] + 8); \
else \
{ \
u32 current_instruction = read_memory16(reg[REG_PC] + 2); \
u32 current_instruction = read_memory16(reg[REG_PC] + 4); \
value = current_instruction | (current_instruction << 16); \
} \

4
mips/mips_emit.h
View File

@ -1197,7 +1197,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
#define arm_access_memory_load(mem_type) \
cycle_count += 2; \
mips_emit_jal(mips_absolute_offset(execute_load_##mem_type)); \
generate_load_pc(reg_a1, (pc + 8)); \
generate_load_pc(reg_a1, (pc)); \
generate_store_reg(reg_rv, rd); \
check_store_reg_pc_no_flags(rd) \
@ -1562,7 +1562,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
#define thumb_access_memory_load(mem_type, reg_rd) \
cycle_count += 2; \
mips_emit_jal(mips_absolute_offset(execute_load_##mem_type)); \
generate_load_pc(reg_a1, (pc + 4)); \
generate_load_pc(reg_a1, (pc)); \
generate_store_reg(reg_rv, reg_rd) \
#define thumb_access_memory_store(mem_type, reg_rd) \