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Fix ARM dynarec 

Turns out there were a couple of very interesting and hard to track
bugs. A missing comma made the reg list too short, leaving the 31th
element at the mercy of the linker ordering algorithm, which seems to
work in some cases depending on the compiler version.
Also the cache flush code seemed not to work on my machine (OGA),
not sure why it wored in the past :/
This commit is contained in:
David Guillen Fandos 2021-02-10 02:46:45 +01:00
parent f70d8534a1
commit 7aaa280b9f
2 changed files with 4 additions and 10 deletions
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4
arm/arm_emit.h
View File

@ -174,7 +174,7 @@ s32 arm_register_allocation[] =
reg_x4, /* GBA r12 */
mem_reg, /* GBA r13 */
reg_x5, /* GBA r14 */
reg_a0 /* GBA r15 */
mem_reg, /* GBA r15 */
mem_reg,
mem_reg,
@ -211,7 +211,7 @@ s32 thumb_register_allocation[] =
mem_reg, /* GBA r12 */
mem_reg, /* GBA r13 */
mem_reg, /* GBA r14 */
reg_a0 /* GBA r15 */
mem_reg, /* GBA r15 */
mem_reg,
mem_reg,

10
cpu_threaded.c
View File

@ -272,17 +272,11 @@ extern u8 bit_count[256];
#define invalidate_icache_region(addr, size) (void)0
#elif defined(ARM_ARCH)
static int sys_cacheflush(void *addr, unsigned long size)
static void sys_cacheflush(void *addr, unsigned long size)
{
void *start = (void*)addr;
void *end = (void*)(char *)addr + size;
register const unsigned char *r0 asm("r0") = start;
register const unsigned char *r1 asm("r1") = end;
register const int r2 asm("r2") = 0;
register const int r7 asm("r7") = 0xf0002;
asm volatile ("svc 0x0" :: "r" (r0), "r" (r1), "r" (r2), "r" (r7));
return -1;
__clear_cache(start, end);
}
#define translate_invalidate_dcache_one(which) \