wip: more jit endian swap macro
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1 changed files with 58 additions and 45 deletions
103
mips/mips_emit.h
103
mips/mips_emit.h
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@ -2016,6 +2016,60 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
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mips_emit_jr(mips_reg_ra); \
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mips_emit_nop();
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#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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/*
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400230: 00042e00 sll a1,a0,0x18
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400234: 00041602 srl v0,a0,0x18
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400238: 00041a02 srl v1,a0,0x8
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40023c: 00451025 or v0,v0,a1
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400240: 3063ff00 andi v1,v1,0xff00
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400244: 00431025 or v0,v0,v1
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400248: 00042200 sll a0,a0,0x8
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40024c: 3c0300ff lui v1,0xff
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400250: 00832024 and a0,a0,v1
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400258: 00441025 or v0,v0,a0
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*/
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#define emit_eswap32(r) \
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mips_emit_sll(reg_temp, r, 24); \
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mips_emit_srl(mips_reg_k0, r, 24); \
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mips_emit_srl(mips_reg_k1, r, 8); \
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mips_emit_or(mips_reg_k0, mips_reg_k0, reg_temp); \
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mips_emit_andi(mips_reg_k1, mips_reg_k1, 0xff00); \
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mips_emit_or(mips_reg_k0, mips_reg_k0, mips_reg_k1); \
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mips_emit_sll(r, r, 8); \
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mips_emit_lui(mips_reg_k1, 0xff); \
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mips_emit_and(r, r, mips_reg_k1); \
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mips_emit_or(r, mips_reg_k0, r)
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/*
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this first part's signext stuff... maybe not always necessary here?
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400218: 00021400 sll v0,v0,0x10
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40021c: 00021403 sra v0,v0,0x10
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400220: 3042ffff andi v0,v0,0xffff
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400224: 00021a00 sll v1,v0,0x8
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400228: 00021202 srl v0,v0,0x8
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40022c: 00621025 or v0,v1,v0
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400230: 3042ffff andi v0,v0,0xffff
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*/
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#define emit_eswap16(r, sext) \
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mips_emit_sll(reg_temp, r, 8); \
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mips_emit_srl(r, r, 8); \
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mips_emit_or(r, reg_temp, r); \
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mips_emit_andi(r, r, 0xffff); \
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if (sext) { \
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mips_emit_sll(r, r, 16); \
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mips_emit_sra(r, r, 16); \
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}
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#else
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#define emit_eswap32(r)
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#define emit_eswap16(r, sext)
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#endif
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// Pointer table to stubs, indexed by type and region
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extern u32 tmemld[11][16];
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extern u32 tmemst[ 4][16];
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@ -2050,30 +2104,7 @@ static void emit_mem_access_loadop(
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switch (size) {
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case 2:
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mips_emit_lw(reg_rv, reg_rv, (base_addr & 0xffff));
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/*
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400230: 00042e00 sll a1,a0,0x18
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400234: 00041602 srl v0,a0,0x18
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400238: 00041a02 srl v1,a0,0x8
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40023c: 00451025 or v0,v0,a1
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400240: 3063ff00 andi v1,v1,0xff00
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400244: 00431025 or v0,v0,v1
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400248: 00042200 sll a0,a0,0x8
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40024c: 3c0300ff lui v1,0xff
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400250: 00832024 and a0,a0,v1
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400258: 00441025 or v0,v0,a0
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*/
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#ifdef NINTENDO64 // byte order swap
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mips_emit_sll(reg_temp, reg_rv, 24);
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mips_emit_srl(mips_reg_k1, reg_rv, 24);
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mips_emit_srl(mips_reg_k2, reg_rv, 8);
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mips_emit_or(mips_reg_k1, mips_reg_k1, reg_temp);
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mips_emit_andi(mips_reg_k2, mips_reg_k2, 0xff00);
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mips_emit_or(mips_reg_k1, mips_reg_k1, mips_reg_k2);
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mips_emit_sll(reg_rv, reg_rv, 8);
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mips_emit_lui(mips_reg_k2, 0xff);
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mips_emit_and(reg_rv, reg_rv, mips_reg_k2);
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mips_emit_or(reg_rv, mips_reg_k1, reg_rv);
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#endif
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emit_eswap32(reg_rv);
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break;
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case 1:
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if (signext) {
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@ -2086,27 +2117,7 @@ static void emit_mem_access_loadop(
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} else {
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mips_emit_lhu(reg_rv, reg_rv, (base_addr & 0xffff));
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}
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/*
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this first part's signext stuff... maybe not always necessary here?
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400218: 00021400 sll v0,v0,0x10
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40021c: 00021403 sra v0,v0,0x10
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400220: 3042ffff andi v0,v0,0xffff
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400224: 00021a00 sll v1,v0,0x8
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400228: 00021202 srl v0,v0,0x8
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40022c: 00621025 or v0,v1,v0
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400230: 3042ffff andi v0,v0,0xffff
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*/
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#ifdef NINTENDO64
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mips_emit_sll(reg_temp, reg_rv, 8);
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mips_emit_srl(reg_rv, reg_rv, 8);
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mips_emit_or(reg_rv, reg_temp, reg_rv);
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mips_emit_andi(reg_rv, reg_rv, 0xffff);
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if (signext) {
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mips_emit_sll(reg_rv, reg_rv, 16);
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mips_emit_sra(reg_rv, reg_rv, 16);
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}
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#endif
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emit_eswap16(reg_rv, signext);
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break;
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default:
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if (signext) {
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@ -2381,8 +2392,10 @@ static void emit_pmemst_stub(
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// Store the data (delay slot from the SMC branch)
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if (realsize == 2) {
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emit_eswap32(reg_a1);
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mips_emit_sw(reg_a1, reg_rv, base_addr);
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} else if (realsize == 1) {
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emit_eswap16(reg_a1, false);
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mips_emit_sh(reg_a1, reg_rv, base_addr);
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} else {
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mips_emit_sb(reg_a1, reg_rv, base_addr);
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