Add preliminary support for PS2 devices
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12
Makefile
12
Makefile
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@ -396,6 +396,18 @@ else ifeq ($(platform), mips64n32)
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HAVE_DYNAREC := 1
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HAVE_DYNAREC := 1
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CPU_ARCH := mips
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CPU_ARCH := mips
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# PS2
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else ifeq ($(platform), ps2)
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TARGET := $(TARGET_NAME)_libretro_$(platform).a
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CC = mips64r5900el-ps2-elf-gcc$(EXE_EXT)
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AR = mips64r5900el-ps2-elf-ar$(EXE_EXT)
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CFLAGS += -fomit-frame-pointer -ffast-math
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CFLAGS += -DPS2 -DUSE_XBGR1555_FORMAT -DROM_BUFFER_SIZE=12
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CFLAGS += -D_EE -I$(PS2SDK)/ee/include/ -I$(PS2SDK)/common/include/
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HAVE_DYNAREC = 1
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CPU_ARCH := mips
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STATIC_LINKING = 1
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# emscripten
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# emscripten
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else ifeq ($(platform), emscripten)
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else ifeq ($(platform), emscripten)
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TARGET := $(TARGET_NAME)_libretro_$(platform).bc
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TARGET := $(TARGET_NAME)_libretro_$(platform).bc
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@ -25,6 +25,8 @@
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#if defined(VITA)
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#if defined(VITA)
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#include <psp2/kernel/sysmem.h>
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#include <psp2/kernel/sysmem.h>
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#include <stdio.h>
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#include <stdio.h>
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#elif defined(PS2)
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#include <kernel.h>
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#endif
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#endif
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u8 *last_rom_translation_ptr = NULL;
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u8 *last_rom_translation_ptr = NULL;
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@ -212,6 +214,11 @@ extern u8 bit_count[256];
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sceKernelDcacheWritebackRange(baseaddr, ((char*)endptr) - ((char*)baseaddr));
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sceKernelDcacheWritebackRange(baseaddr, ((char*)endptr) - ((char*)baseaddr));
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sceKernelIcacheInvalidateRange(baseaddr, ((char*)endptr) - ((char*)baseaddr));
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sceKernelIcacheInvalidateRange(baseaddr, ((char*)endptr) - ((char*)baseaddr));
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}
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}
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#elif defined(PS2)
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void platform_cache_sync(void *baseaddr, void *endptr) {
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FlushCache(0); // Dcache flush
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FlushCache(2); // Icache invalidate
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}
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#elif defined(VITA)
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#elif defined(VITA)
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void platform_cache_sync(void *baseaddr, void *endptr) {
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void platform_cache_sync(void *baseaddr, void *endptr) {
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sceKernelSyncVMDomain(sceBlock, baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
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sceKernelSyncVMDomain(sceBlock, baseaddr, ((char*)endptr) - ((char*)baseaddr) + 64);
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@ -3205,13 +3205,15 @@ static void emit_phand(
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mips_emit_lw(reg_temp, reg_temp, tbloff2); // Get opcode from 2nd table
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mips_emit_lw(reg_temp, reg_temp, tbloff2); // Get opcode from 2nd table
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mips_emit_sw(reg_temp, mips_reg_ra, -8); // Patch instruction!
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mips_emit_sw(reg_temp, mips_reg_ra, -8); // Patch instruction!
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#ifdef PSP
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#if defined(PSP)
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mips_emit_cache(0x1A, mips_reg_ra, -8);
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mips_emit_cache(0x1A, mips_reg_ra, -8);
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mips_emit_jr(reg_rv); // Jump directly to target for speed
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mips_emit_jr(reg_rv); // Jump directly to target for speed
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mips_emit_cache(0x08, mips_reg_ra, -8);
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mips_emit_cache(0x08, mips_reg_ra, -8);
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#else
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#else
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mips_emit_jr(reg_rv);
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mips_emit_jr(reg_rv);
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mips_emit_synci(mips_reg_ra, -8);
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#ifdef MIPS_HAS_R2_INSTS
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mips_emit_synci(mips_reg_ra, -8);
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#endif
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#endif
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#endif
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// Round up handlers to 16 instructions for easy addressing
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// Round up handlers to 16 instructions for easy addressing
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