Reimplement cache invalidation code
This commit is contained in:
twinaphex
parent
97166d5cbd
commit
5b59ef3acc
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@ -32,9 +32,7 @@ endif
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endif
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endif
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# Special optimized routines
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ifeq ($(CPU_ARCH), arm)
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ifeq ($(CPU_ARCH), arm)
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SOURCES_C += $(CORE_DIR)/arm/warm.c
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SOURCES_ASM += $(CORE_DIR)/arm/video_blend.S
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SOURCES_ASM += $(CORE_DIR)/arm/video_blend.S
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endif
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endif
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@ -636,33 +636,8 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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} \
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} \
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} \
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} \
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u8 *last_rom_translation_ptr = NULL;
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u8 *last_ram_translation_ptr = NULL;
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u8 *last_bios_translation_ptr = NULL;
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#define translate_invalidate_dcache_one(which) \
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if (which##_translation_ptr > last_##which##_translation_ptr) \
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{ \
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warm_cache_op_range(WOP_D_CLEAN, last_##which##_translation_ptr, \
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which##_translation_ptr - last_##which##_translation_ptr); \
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warm_cache_op_range(WOP_I_INVALIDATE, last_##which##_translation_ptr, 32);\
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last_##which##_translation_ptr = which##_translation_ptr; \
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}
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#define translate_invalidate_dcache() \
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{ \
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translate_invalidate_dcache_one(rom) \
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translate_invalidate_dcache_one(ram) \
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translate_invalidate_dcache_one(bios) \
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}
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#define invalidate_icache_region(addr, size) \
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warm_cache_op_range(WOP_I_INVALIDATE, addr, size)
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#define block_prologue_size 0
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#define block_prologue_size 0
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// It should be okay to still generate result flags, spsr will overwrite them.
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// It should be okay to still generate result flags, spsr will overwrite them.
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// This is pretty infrequent (returning from interrupt handlers, et al) so
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// This is pretty infrequent (returning from interrupt handlers, et al) so
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// probably not worth optimizing for.
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// probably not worth optimizing for.
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67
arm/warm.c
67
arm/warm.c
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@ -1,67 +0,0 @@
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/*
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* wARM - exporting ARM processor specific privileged services to userspace
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* userspace part
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*
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* Copyright (c) Gražvydas "notaz" Ignotas, 2009
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the organization nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include <sys/types.h>
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#include <sys/stat.h>
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#include <unistd.h>
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#include <fcntl.h>
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#include <sys/syscall.h>
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#include <errno.h>
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#include "warm.h"
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static void sys_cacheflush(void *start, void *end)
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{
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#ifdef __ARM_EABI__
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/* EABI version */
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int num = __ARM_NR_cacheflush;
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__asm__("mov r0, %0 ;"
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"mov r1, %1 ;"
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"mov r2, #0 ;"
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"mov r7, %2 ;"
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"swi 0" : : "r" (start), "r" (end), "r" (num)
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: "r0", "r1", "r2", "r3", "r7");
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#else
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/* OABI */
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__asm__("mov r0, %0 ;"
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"mov r1, %1 ;"
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"mov r2, #0 ;"
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"swi %2" : : "r" (start), "r" (end), "i" __ARM_NR_cacheflush
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: "r0", "r1", "r2", "r3");
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#endif
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}
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int warm_cache_op_range(int op, void *addr, unsigned long size)
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{
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sys_cacheflush(addr, (char *)addr + size);
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return -1;
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}
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53
arm/warm.h
53
arm/warm.h
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@ -1,53 +0,0 @@
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/*
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* wARM - exporting ARM processor specific privileged services to userspace
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* library functions
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*
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* Copyright (c) Gražvydas "notaz" Ignotas, 2009
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the organization nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __WARM_H__
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#define __WARM_H__ 1
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/* cache operations (warm_cache_op_*):
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* o clean - write dirty data to memory, but also leave in cache.
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* o invalidate - throw away everything in cache, losing dirty data.
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*
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* Write buffer is always drained, no ops will only drain WB
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*/
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#define WOP_D_CLEAN (1 << 0)
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#define WOP_D_INVALIDATE (1 << 1)
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#define WOP_I_INVALIDATE (1 << 2)
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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int warm_cache_op_range(int ops, void *virt_addr, unsigned long size);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __WARM_H__ */
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4
common.h
4
common.h
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@ -210,8 +210,4 @@ typedef u32 fixed8_24;
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#include "main.h"
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#include "main.h"
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#include "cheats.h"
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#include "cheats.h"
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#ifdef ARM_ARCH
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#include "arm/warm.h"
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#endif
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#endif
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#endif
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@ -23,6 +23,10 @@
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#include "common.h"
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#include "common.h"
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u8 *last_rom_translation_ptr = NULL;
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u8 *last_ram_translation_ptr = NULL;
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u8 *last_bios_translation_ptr = NULL;
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#if defined(HAVE_MMAP)
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#if defined(HAVE_MMAP)
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u8* rom_translation_cache;
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u8* rom_translation_cache;
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u8* ram_translation_cache;
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u8* ram_translation_cache;
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@ -218,6 +222,51 @@ extern u8 bit_count[256];
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#endif
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#endif
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/* Cache invalidation */
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#if defined(PSP_BUILD)
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#define translate_invalidate_dcache() sceKernelDcacheWritebackAll()
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#elif defined(ARM_ARCH)
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static int sys_cacheflush(void *addr, unsigned long size)
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{
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void *start = (void*)addr;
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void *end = (void*)(char *)addr + size;
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register const unsigned char *r0 asm("r0") = start;
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register const unsigned char *r1 asm("r1") = end;
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register const int r2 asm("r2") = 0;
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register const int r7 asm("r7") = 0xf0002;
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asm volatile ("svc 0x0" :: "r" (r0), "r" (r1), "r" (r2), "r" (r7));
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return -1;
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}
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#define translate_invalidate_dcache_one(which) \
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if (which##_translation_ptr > last_##which##_translation_ptr) \
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{ \
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sys_cacheflush(last_##which##_translation_ptr, \
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which##_translation_ptr - last_##which##_translation_ptr); \
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sys_cacheflush(last_##which##_translation_ptr, 32);\
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last_##which##_translation_ptr = which##_translation_ptr; \
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}
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#define translate_invalidate_dcache() \
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{ \
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translate_invalidate_dcache_one(rom) \
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translate_invalidate_dcache_one(ram) \
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translate_invalidate_dcache_one(bios) \
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}
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#define invalidate_icache_region(addr, size) (void)0
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#else
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#define translate_invalidate_dcache() (void)0
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#define invalidate_icache_region(addr, size) (void)0
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#endif
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/* End of Cache invalidation */
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#define check_pc_region(pc) \
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#define check_pc_region(pc) \
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new_pc_region = (pc >> 15); \
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new_pc_region = (pc >> 15); \
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@ -3632,13 +3681,8 @@ void flush_translation_cache_ram(void)
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flush_ram_count, reg[REG_PC], iwram_code_min, iwram_code_max,
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flush_ram_count, reg[REG_PC], iwram_code_min, iwram_code_max,
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ewram_code_min, ewram_code_max); */
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ewram_code_min, ewram_code_max); */
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#if defined(ARM_ARCH) || defined(MIPS_ARCH)
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invalidate_icache_region(ram_translation_cache, (ram_translation_ptr - ram_translation_cache) + 0x100);
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invalidate_icache_region(ram_translation_cache,
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(ram_translation_ptr - ram_translation_cache) + 0x100);
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#endif
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#ifdef ARM_ARCH
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last_ram_translation_ptr = ram_translation_cache;
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last_ram_translation_ptr = ram_translation_cache;
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#endif
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ram_translation_ptr = ram_translation_cache;
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ram_translation_ptr = ram_translation_cache;
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ram_block_tag_top = 0x0101;
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ram_block_tag_top = 0x0101;
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if(iwram_code_min != 0xFFFFFFFF)
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if(iwram_code_min != 0xFFFFFFFF)
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@ -3673,9 +3717,7 @@ void flush_translation_cache_ram(void)
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else
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else
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{
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{
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for(i = ewram_code_min_page + 1; i < ewram_code_max_page; i++)
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for(i = ewram_code_min_page + 1; i < ewram_code_max_page; i++)
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{
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memset(ewram + (i * 0x10000), 0, 0x8000);
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memset(ewram + (i * 0x10000), 0, 0x8000);
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}
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memset(ewram, 0, ewram_code_max_offset);
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memset(ewram, 0, ewram_code_max_offset);
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}
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}
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@ -3689,30 +3731,23 @@ void flush_translation_cache_ram(void)
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void flush_translation_cache_rom(void)
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void flush_translation_cache_rom(void)
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{
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{
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#if defined(ARM_ARCH) || defined(MIPS_ARCH)
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invalidate_icache_region(rom_translation_cache, rom_translation_ptr - rom_translation_cache + 0x100);
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invalidate_icache_region(rom_translation_cache,
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rom_translation_ptr - rom_translation_cache + 0x100);
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#endif
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#ifdef ARM_ARCH
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last_rom_translation_ptr = rom_translation_cache;
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#endif
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last_rom_translation_ptr = rom_translation_cache;
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rom_translation_ptr = rom_translation_cache;
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rom_translation_ptr = rom_translation_cache;
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memset(rom_branch_hash, 0, sizeof(rom_branch_hash));
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memset(rom_branch_hash, 0, sizeof(rom_branch_hash));
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}
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}
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void flush_translation_cache_bios(void)
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void flush_translation_cache_bios(void)
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{
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{
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#if defined(ARM_ARCH) || defined(MIPS_ARCH)
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invalidate_icache_region(bios_translation_cache, bios_translation_ptr - bios_translation_cache + 0x100);
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invalidate_icache_region(bios_translation_cache,
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bios_translation_ptr - bios_translation_cache + 0x100);
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#endif
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#ifdef ARM_ARCH
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last_bios_translation_ptr = bios_translation_cache;
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#endif
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bios_block_tag_top = 0x0101;
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bios_block_tag_top = 0x0101;
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last_bios_translation_ptr = bios_translation_cache;
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bios_translation_ptr = bios_translation_cache;
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bios_translation_ptr = bios_translation_cache;
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memset(bios_rom + 0x4000, 0, 0x4000);
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memset(bios_rom + 0x4000, 0, 0x4000);
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}
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}
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@ -641,9 +641,6 @@ u32 arm_to_mips_reg[] =
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mips_emit_nop(); \
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mips_emit_nop(); \
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generate_load_imm(reg_pc, stored_pc) \
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generate_load_imm(reg_pc, stored_pc) \
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#define translate_invalidate_dcache() \
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sceKernelDcacheWritebackAll() \
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#define block_prologue_size 8
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#define block_prologue_size 8
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#define check_generate_n_flag \
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#define check_generate_n_flag \
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@ -492,9 +492,6 @@ typedef enum
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#define generate_block_extra_vars_thumb() \
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#define generate_block_extra_vars_thumb() \
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#define translate_invalidate_dcache() \
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#define block_prologue_size 0
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#define block_prologue_size 0
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#define calculate_z_flag(dest) \
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#define calculate_z_flag(dest) \
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