Fix JIT section in MIPS (+ minor cleanup)
This seems to be an issue on some devices, better place it in .bss unless we are running on Linux.
This commit is contained in:
David Guillen Fandos
parent
d41d5a4af4
commit
3790b233f1
113
psp/mips_stub.S
113
psp/mips_stub.S
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@ -31,39 +31,19 @@
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#define REG_S sw
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#endif
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#define defsymbl(symbol) \
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.type symbol, %function ;\
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.global symbol ; \
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symbol:
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#define defobj(symbol) \
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.type symbol, %object ;\
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.global symbol ; \
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symbol:
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.align 4
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.global mips_update_gba
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.global mips_indirect_branch_arm
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.global mips_indirect_branch_thumb
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.global mips_indirect_branch_dual
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.global execute_read_cpsr
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.global execute_read_spsr
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.global execute_swi
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.global execute_spsr_restore
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.global execute_store_cpsr
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.global execute_store_spsr
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.global execute_lsl_flags_reg
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.global execute_lsr_flags_reg
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.global execute_asr_flags_reg
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.global execute_arm_translate_internal
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.global palette_ram
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.global palette_ram_converted
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.global oam_ram
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.global mips_lookup_pc
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.global smc_write
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.global mips_cheat_hook
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.global write_io_epilogue
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.global memory_map_read
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.global tmemld
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.global tmemst
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.global thnjal
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.global reg
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.global spsr
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.global reg_mode
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.global oam_update
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# MIPS register layout:
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# $0 - constant zero
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@ -252,7 +232,7 @@
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# This gets called every time the cycle counter runs out
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# (checked at every branch/jump)
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mips_update_gba:
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defsymbl(mips_update_gba)
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sw $4, REG_PC($16) # current PC = $4
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sw $ra, REG_SAVE2($16) # save return addr
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@ -279,7 +259,7 @@ mips_update_gba:
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# Processes cheats whenever we hit the master PC
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mips_cheat_hook:
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defsymbl(mips_cheat_hook)
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sw $ra, REG_SAVE2($16)
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save_registers
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cfncall process_cheats, 8
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@ -310,21 +290,21 @@ return_to_main:
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# $4: GBA address to branch to
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mips_indirect_branch_arm:
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defsymbl(mips_indirect_branch_arm)
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save_registers
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cfncall block_lookup_address_arm, 1
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restore_registers
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jr $2 # $2 = value returned
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nop
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mips_indirect_branch_thumb:
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defsymbl(mips_indirect_branch_thumb)
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save_registers
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cfncall block_lookup_address_thumb, 2
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restore_registers
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jr $2 # $2 = value returned
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nop
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mips_indirect_branch_dual:
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defsymbl(mips_indirect_branch_dual)
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save_registers
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cfncall block_lookup_address_dual, 3
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nop
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@ -333,7 +313,7 @@ mips_indirect_branch_dual:
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nop
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write_io_epilogue:
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defsymbl(write_io_epilogue)
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beq $2, $0, no_alert # 0 means nothing happened
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addiu $4, $2, -2 # see if return value is 2 (delay slot)
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beq $4, $0, smc_dma # is it an SMC alert? (return value = 2)
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@ -377,12 +357,11 @@ smc_dma:
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j lookup_pc
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nop
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smc_write:
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defsymbl(smc_write)
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save_registers
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sw $6, REG_PC($16) # save PC
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cfncall flush_translation_cache_ram, 4
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mips_lookup_pc:
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lookup_pc:
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lw $2, REG_CPSR($16) # $2 = cpsr
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andi $2, $2, 0x20 # isolate mode bit
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@ -405,14 +384,14 @@ lookup_pc_arm:
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# Return the current cpsr
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execute_read_cpsr:
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defsymbl(execute_read_cpsr)
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collapse_flags # fold flags into cpsr, put cpsr into $2
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jr $ra # return
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nop
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# Return the current spsr
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execute_read_spsr:
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defsymbl(execute_read_spsr)
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lw $1, CPU_MODE($16) # $1 = cpu_mode
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sll $1, $1, 2 # adjust to word offset size
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addu $2, $1, $16
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@ -422,7 +401,7 @@ execute_read_spsr:
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# Switch into SWI, has to collapse flags
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# $4: Current pc
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execute_swi:
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defsymbl(execute_swi)
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sw $ra, REG_SAVE3($16)
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sw $4, SUPERVISOR_LR($16) # store next PC in the supervisor's LR
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collapse_flags # get cpsr in $2
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@ -442,7 +421,7 @@ execute_swi:
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# $4: pc to restore to
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# returns in $4
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execute_spsr_restore:
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defsymbl(execute_spsr_restore)
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lw $1, CPU_MODE($16) # $1 = cpu_mode
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beq $1, $0, no_spsr_restore # only restore if the cpu isn't usermode
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@ -468,7 +447,7 @@ no_spsr_restore:
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# $5: store mask
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# $6: current PC
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execute_store_cpsr:
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defsymbl(execute_store_cpsr)
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and $1, $4, $5 # $1 = new_cpsr & store_mask
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lw $2, REG_CPSR($16) # $2 = current cpsr
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nor $4, $5, $0 # $4 = ~store_mask
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@ -500,7 +479,7 @@ changed_pc_cpsr:
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# $4: new spsr
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# $5: store mask
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execute_store_spsr:
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defsymbl(execute_store_spsr)
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lw $1, CPU_MODE($16) # $1 = cpu_mode
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sll $1, $1, 2 # adjust to word offset size
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addu $1, $1, $16
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@ -515,7 +494,7 @@ execute_store_spsr:
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# $4: value
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# $5: shift
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execute_lsl_flags_reg:
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defsymbl(execute_lsl_flags_reg)
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beq $5, $0, lsl_shift_zero # is the shift zero?
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sltiu $1, $5, 32 # $1 = (shift < 32) (delay)
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beq $1, $0, lsl_shift_high # is the shift >= 32?
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@ -541,7 +520,7 @@ lsl_shift_done:
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addu $4, $0, $0 # value = 0 no matter what
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execute_lsr_flags_reg:
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defsymbl(execute_lsr_flags_reg)
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beq $5, $0, lsr_shift_zero # is the shift zero?
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sltiu $1, $5, 32 # $1 = (shift < 32) (delay)
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beq $1, $0, lsr_shift_high # is the shift >= 32?
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@ -566,7 +545,7 @@ lsr_shift_done:
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addu $4, $0, $0 # value = 0 no matter what
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execute_asr_flags_reg:
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defsymbl(execute_asr_flags_reg)
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beq $5, $0, asr_shift_zero # is the shift zero?
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sltiu $1, $5, 32 # $1 = (shift < 32) (delay)
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beq $1, $0, asr_shift_high # is the shift >= 32?
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@ -588,7 +567,7 @@ asr_shift_high:
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# $4: cycle counter argument
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# $5: pointer to reg
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execute_arm_translate_internal:
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defsymbl(execute_arm_translate_internal)
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addiu $sp, $sp, -112 # Store the main thread context
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REG_S $s0, 4*SZREG($sp)
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@ -634,24 +613,24 @@ execute_arm_translate_internal:
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.data
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.align 6
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memory_map_read:
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defobj(memory_map_read)
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.space 0x8000
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# memory_map_read is immediately before arm_reg on purpose (offset used
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# to access it, via lw op). We do not use write though.
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reg:
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defobj(reg)
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.space 0x100
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# Placed here for easy access
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palette_ram:
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defobj(palette_ram)
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.space 0x400
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palette_ram_converted:
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defobj(palette_ram_converted)
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.space 0x400
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oam_ram:
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defobj(oam_ram)
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.space 0x400
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spsr:
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defobj(spsr)
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.space 24 # u32[6]
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reg_mode:
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defobj(reg_mode)
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.space 196 # u32[7][7];
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# Here we store:
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@ -659,11 +638,11 @@ reg_mode:
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# void *tmemst[ 4][16]; # 3 types of stores
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# Essentially a list of pointers to the different mem load handlers
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# Keep them close for a fast patcher.
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tmemld:
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defobj(tmemld)
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.space 704
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tmemst:
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defobj(tmemst)
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.space 256
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thnjal:
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defobj(thnjal)
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.space 960
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fnptrs:
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.long update_gba # 0
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@ -680,17 +659,19 @@ fnptrs:
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# Make this section executable!
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.text
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.section .jit,"awx",%nobits
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#if defined(PSP) || defined(PS2)
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.section .bss
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#else
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# Need to mark the section as awx (for Linux)
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.section .jit,"awx",%nobits
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#endif
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.align 2
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.global stub_arena
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.global rom_translation_cache
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.global ram_translation_cache
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stub_arena:
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defsymbl(stub_arena)
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.space STUB_ARENA_SIZE
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rom_translation_cache:
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defsymbl(rom_translation_cache)
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.space ROM_TRANSLATION_CACHE_SIZE
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ram_translation_cache:
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defsymbl(ram_translation_cache)
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.space RAM_TRANSLATION_CACHE_SIZE
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#endif
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