Small optimization (~2-4%) and whitespace cleanup!
Cleans up a ton of whitespace in cpu.c (like 100KB!) and improves readability of some massive decode statements. Added an optimization for PC-relative loads (pool load) in ROM (since it's read only and cannot possibily change) that directly emits an immediate load. This is way faster, specially in MIPS/x86, ARM can be even faster if we rewrite the immediate load macros to also use a pool.
This commit is contained in:
David Guillen Fandos
parent
7877a8888b
commit
37430f22c5
7 changed files with 1980 additions and 2721 deletions
1
Makefile
1
Makefile
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@ -376,6 +376,7 @@ else ifeq ($(platform), mips32)
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SHARED := -shared -nostdlib -Wl,--version-script=link.T
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fpic := -fPIC -DPIC
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CFLAGS += -fomit-frame-pointer -ffast-math -march=mips32 -mtune=mips32r2 -mhard-float
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CFLAGS += -fno-caller-saves
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HAVE_DYNAREC := 1
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CPU_ARCH := mips
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@ -319,7 +319,7 @@ u32 arm_disect_imm_32bit(u32 imm, u32 *stores, u32 *rotations)
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#define generate_load_pc(ireg, new_pc) \
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arm_load_imm_32bit(ireg, new_pc) \
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arm_load_imm_32bit(ireg, (new_pc)) \
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#define generate_load_imm(ireg, imm, imm_ror) \
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ARM_MOV_REG_IMM(0, ireg, imm, imm_ror) \
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@ -1658,6 +1658,10 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
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/* Operation types: imm, mem_reg, mem_imm */
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#define thumb_load_pc_pool_const(reg_rd, value) \
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generate_load_pc(reg_a0, (value)); \
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generate_store_reg(reg_a0, reg_rd)
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#define thumb_access_memory_load(mem_type, _rd) \
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cycle_count += 2; \
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generate_function_call(execute_load_##mem_type); \
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384
cpu_threaded.c
384
cpu_threaded.c
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@ -1705,8 +1705,9 @@ void translate_icache_sync() {
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last_opcode = opcode; \
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opcode = address16(pc_address_block, (pc & 0x7FFF)); \
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emit_trace_thumb_instruction(pc); \
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u8 hiop = opcode >> 8; \
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\
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switch((opcode >> 8) & 0xFF) \
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switch(hiop) \
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{ \
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case 0x00 ... 0x07: \
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/* LSL rd, rs, imm */ \
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@ -1743,165 +1744,45 @@ void translate_icache_sync() {
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thumb_data_proc(add_sub_imm, subs, imm, rd, rs, imm); \
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break; \
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\
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case 0x20: \
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/* MOV r0, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 0, imm); \
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break; \
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/* MOV r0..7, imm */ \
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case 0x20: thumb_data_proc_unary(imm, movs, imm, 0, imm); break; \
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case 0x21: thumb_data_proc_unary(imm, movs, imm, 1, imm); break; \
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case 0x22: thumb_data_proc_unary(imm, movs, imm, 2, imm); break; \
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case 0x23: thumb_data_proc_unary(imm, movs, imm, 3, imm); break; \
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case 0x24: thumb_data_proc_unary(imm, movs, imm, 4, imm); break; \
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case 0x25: thumb_data_proc_unary(imm, movs, imm, 5, imm); break; \
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case 0x26: thumb_data_proc_unary(imm, movs, imm, 6, imm); break; \
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case 0x27: thumb_data_proc_unary(imm, movs, imm, 7, imm); break; \
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\
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case 0x21: \
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/* MOV r1, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 1, imm); \
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break; \
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/* CMP r0, imm */ \
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case 0x28: thumb_data_proc_test(imm, cmp, imm, 0, imm); break; \
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case 0x29: thumb_data_proc_test(imm, cmp, imm, 1, imm); break; \
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case 0x2A: thumb_data_proc_test(imm, cmp, imm, 2, imm); break; \
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case 0x2B: thumb_data_proc_test(imm, cmp, imm, 3, imm); break; \
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case 0x2C: thumb_data_proc_test(imm, cmp, imm, 4, imm); break; \
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case 0x2D: thumb_data_proc_test(imm, cmp, imm, 5, imm); break; \
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case 0x2E: thumb_data_proc_test(imm, cmp, imm, 6, imm); break; \
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case 0x2F: thumb_data_proc_test(imm, cmp, imm, 7, imm); break; \
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\
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case 0x22: \
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/* MOV r2, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 2, imm); \
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break; \
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/* ADD r0..7, imm */ \
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case 0x30: thumb_data_proc(imm, adds, imm, 0, 0, imm); break; \
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case 0x31: thumb_data_proc(imm, adds, imm, 1, 1, imm); break; \
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case 0x32: thumb_data_proc(imm, adds, imm, 2, 2, imm); break; \
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case 0x33: thumb_data_proc(imm, adds, imm, 3, 3, imm); break; \
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case 0x34: thumb_data_proc(imm, adds, imm, 4, 4, imm); break; \
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case 0x35: thumb_data_proc(imm, adds, imm, 5, 5, imm); break; \
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case 0x36: thumb_data_proc(imm, adds, imm, 6, 6, imm); break; \
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case 0x37: thumb_data_proc(imm, adds, imm, 7, 7, imm); break; \
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\
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case 0x23: \
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/* MOV r3, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 3, imm); \
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break; \
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\
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case 0x24: \
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/* MOV r4, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 4, imm); \
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break; \
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\
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case 0x25: \
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/* MOV r5, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 5, imm); \
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break; \
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\
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case 0x26: \
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/* MOV r6, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 6, imm); \
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break; \
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\
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case 0x27: \
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/* MOV r7, imm */ \
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thumb_data_proc_unary(imm, movs, imm, 7, imm); \
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break; \
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\
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case 0x28: \
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/* CMP r0, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 0, imm); \
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break; \
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\
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case 0x29: \
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/* CMP r1, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 1, imm); \
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break; \
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\
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case 0x2A: \
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/* CMP r2, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 2, imm); \
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break; \
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\
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case 0x2B: \
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/* CMP r3, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 3, imm); \
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break; \
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\
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case 0x2C: \
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/* CMP r4, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 4, imm); \
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break; \
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\
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case 0x2D: \
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/* CMP r5, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 5, imm); \
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break; \
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\
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case 0x2E: \
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/* CMP r6, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 6, imm); \
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break; \
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\
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case 0x2F: \
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/* CMP r7, imm */ \
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thumb_data_proc_test(imm, cmp, imm, 7, imm); \
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break; \
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\
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case 0x30: \
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/* ADD r0, imm */ \
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thumb_data_proc(imm, adds, imm, 0, 0, imm); \
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break; \
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\
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case 0x31: \
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/* ADD r1, imm */ \
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thumb_data_proc(imm, adds, imm, 1, 1, imm); \
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break; \
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\
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case 0x32: \
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/* ADD r2, imm */ \
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thumb_data_proc(imm, adds, imm, 2, 2, imm); \
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break; \
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\
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case 0x33: \
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/* ADD r3, imm */ \
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thumb_data_proc(imm, adds, imm, 3, 3, imm); \
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break; \
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\
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case 0x34: \
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/* ADD r4, imm */ \
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thumb_data_proc(imm, adds, imm, 4, 4, imm); \
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break; \
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\
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case 0x35: \
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/* ADD r5, imm */ \
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thumb_data_proc(imm, adds, imm, 5, 5, imm); \
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break; \
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\
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case 0x36: \
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/* ADD r6, imm */ \
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thumb_data_proc(imm, adds, imm, 6, 6, imm); \
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break; \
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\
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case 0x37: \
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/* ADD r7, imm */ \
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thumb_data_proc(imm, adds, imm, 7, 7, imm); \
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break; \
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\
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case 0x38: \
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/* SUB r0, imm */ \
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thumb_data_proc(imm, subs, imm, 0, 0, imm); \
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break; \
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\
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case 0x39: \
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/* SUB r1, imm */ \
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thumb_data_proc(imm, subs, imm, 1, 1, imm); \
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break; \
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\
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case 0x3A: \
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/* SUB r2, imm */ \
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thumb_data_proc(imm, subs, imm, 2, 2, imm); \
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break; \
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\
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case 0x3B: \
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/* SUB r3, imm */ \
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thumb_data_proc(imm, subs, imm, 3, 3, imm); \
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break; \
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\
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case 0x3C: \
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/* SUB r4, imm */ \
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thumb_data_proc(imm, subs, imm, 4, 4, imm); \
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break; \
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\
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case 0x3D: \
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/* SUB r5, imm */ \
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thumb_data_proc(imm, subs, imm, 5, 5, imm); \
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break; \
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\
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case 0x3E: \
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/* SUB r6, imm */ \
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thumb_data_proc(imm, subs, imm, 6, 6, imm); \
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break; \
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\
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case 0x3F: \
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/* SUB r7, imm */ \
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thumb_data_proc(imm, subs, imm, 7, 7, imm); \
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break; \
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/* SUB r0..7, imm */ \
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case 0x38: thumb_data_proc(imm, subs, imm, 0, 0, imm); break; \
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case 0x39: thumb_data_proc(imm, subs, imm, 1, 1, imm); break; \
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case 0x3A: thumb_data_proc(imm, subs, imm, 2, 2, imm); break; \
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case 0x3B: thumb_data_proc(imm, subs, imm, 3, 3, imm); break; \
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case 0x3C: thumb_data_proc(imm, subs, imm, 4, 4, imm); break; \
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case 0x3D: thumb_data_proc(imm, subs, imm, 5, 5, imm); break; \
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case 0x3E: thumb_data_proc(imm, subs, imm, 6, 6, imm); break; \
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case 0x3F: thumb_data_proc(imm, subs, imm, 7, 7, imm); break; \
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\
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case 0x40: \
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switch((opcode >> 6) & 0x03) \
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@ -2023,52 +1904,21 @@ void translate_icache_sync() {
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thumb_bx(); \
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break; \
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\
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case 0x48: \
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/* LDR r0, [pc + imm] */ \
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thumb_access_memory(load, imm, 0, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x49: \
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/* LDR r1, [pc + imm] */ \
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thumb_access_memory(load, imm, 1, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x4A: \
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/* LDR r2, [pc + imm] */ \
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thumb_access_memory(load, imm, 2, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x4B: \
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/* LDR r3, [pc + imm] */ \
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thumb_access_memory(load, imm, 3, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x4C: \
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/* LDR r4, [pc + imm] */ \
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thumb_access_memory(load, imm, 4, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x4D: \
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/* LDR r5, [pc + imm] */ \
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thumb_access_memory(load, imm, 5, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x4E: \
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/* LDR r6, [pc + imm] */ \
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thumb_access_memory(load, imm, 6, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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break; \
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\
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case 0x4F: \
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/* LDR r7, [pc + imm] */ \
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thumb_access_memory(load, imm, 7, 0, 0, pc_relative, \
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(pc & ~2) + (imm * 4) + 4, u32); \
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case 0x48 ... 0x4F: \
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/* LDR r0..7, [pc + imm] */ \
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{ \
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thumb_decode_imm(); \
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u32 rdreg = (hiop & 7); \
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u32 aoff = (pc & ~2) + (imm*4) + 4; \
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/* ROM + same page -> optimize as const load */ \
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if (translation_region == TRANSLATION_REGION_ROM && \
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(((aoff + 4) >> 15) == (pc >> 15))) { \
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u32 value = address32(pc_address_block, (aoff & 0x7FFF)); \
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thumb_load_pc_pool_const(rdreg, value); \
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} else { \
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thumb_access_memory(load, imm, rdreg, 0, 0, pc_relative, aoff, u32);\
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} \
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} \
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break; \
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\
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case 0x50 ... 0x51: \
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@ -2143,165 +1993,77 @@ void translate_icache_sync() {
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thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, (imm * 2), u16); \
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break; \
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\
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/* STR r0..7, [sp + imm] */ \
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case 0x90: \
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/* STR r0, [sp + imm] */ \
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thumb_access_memory(store, imm, 0, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x91: \
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/* STR r1, [sp + imm] */ \
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thumb_access_memory(store, imm, 1, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x92: \
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/* STR r2, [sp + imm] */ \
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thumb_access_memory(store, imm, 2, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x93: \
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/* STR r3, [sp + imm] */ \
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thumb_access_memory(store, imm, 3, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x94: \
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/* STR r4, [sp + imm] */ \
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thumb_access_memory(store, imm, 4, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x95: \
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/* STR r5, [sp + imm] */ \
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thumb_access_memory(store, imm, 5, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x96: \
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/* STR r6, [sp + imm] */ \
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thumb_access_memory(store, imm, 6, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x97: \
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/* STR r7, [sp + imm] */ \
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thumb_access_memory(store, imm, 7, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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/* LDR r0..7, [sp + imm] */ \
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case 0x98: \
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/* LDR r0, [sp + imm] */ \
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thumb_access_memory(load, imm, 0, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x99: \
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/* LDR r1, [sp + imm] */ \
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thumb_access_memory(load, imm, 1, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x9A: \
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/* LDR r2, [sp + imm] */ \
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thumb_access_memory(load, imm, 2, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x9B: \
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/* LDR r3, [sp + imm] */ \
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thumb_access_memory(load, imm, 3, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x9C: \
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/* LDR r4, [sp + imm] */ \
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thumb_access_memory(load, imm, 4, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x9D: \
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/* LDR r5, [sp + imm] */ \
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thumb_access_memory(load, imm, 5, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x9E: \
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/* LDR r6, [sp + imm] */ \
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thumb_access_memory(load, imm, 6, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0x9F: \
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/* LDR r7, [sp + imm] */ \
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thumb_access_memory(load, imm, 7, 13, 0, reg_imm_sp, imm, u32); \
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break; \
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\
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case 0xA0: \
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/* ADD r0, pc, +imm */ \
|
||||
thumb_load_pc(0); \
|
||||
break; \
|
||||
/* ADD r0..7, pc, +imm */ \
|
||||
case 0xA0: thumb_load_pc(0); break; \
|
||||
case 0xA1: thumb_load_pc(1); break; \
|
||||
case 0xA2: thumb_load_pc(2); break; \
|
||||
case 0xA3: thumb_load_pc(3); break; \
|
||||
case 0xA4: thumb_load_pc(4); break; \
|
||||
case 0xA5: thumb_load_pc(5); break; \
|
||||
case 0xA6: thumb_load_pc(6); break; \
|
||||
case 0xA7: thumb_load_pc(7); break; \
|
||||
\
|
||||
case 0xA1: \
|
||||
/* ADD r1, pc, +imm */ \
|
||||
thumb_load_pc(1); \
|
||||
break; \
|
||||
\
|
||||
case 0xA2: \
|
||||
/* ADD r2, pc, +imm */ \
|
||||
thumb_load_pc(2); \
|
||||
break; \
|
||||
\
|
||||
case 0xA3: \
|
||||
/* ADD r3, pc, +imm */ \
|
||||
thumb_load_pc(3); \
|
||||
break; \
|
||||
\
|
||||
case 0xA4: \
|
||||
/* ADD r4, pc, +imm */ \
|
||||
thumb_load_pc(4); \
|
||||
break; \
|
||||
\
|
||||
case 0xA5: \
|
||||
/* ADD r5, pc, +imm */ \
|
||||
thumb_load_pc(5); \
|
||||
break; \
|
||||
\
|
||||
case 0xA6: \
|
||||
/* ADD r6, pc, +imm */ \
|
||||
thumb_load_pc(6); \
|
||||
break; \
|
||||
\
|
||||
case 0xA7: \
|
||||
/* ADD r7, pc, +imm */ \
|
||||
thumb_load_pc(7); \
|
||||
break; \
|
||||
\
|
||||
case 0xA8: \
|
||||
/* ADD r0, sp, +imm */ \
|
||||
thumb_load_sp(0); \
|
||||
break; \
|
||||
\
|
||||
case 0xA9: \
|
||||
/* ADD r1, sp, +imm */ \
|
||||
thumb_load_sp(1); \
|
||||
break; \
|
||||
\
|
||||
case 0xAA: \
|
||||
/* ADD r2, sp, +imm */ \
|
||||
thumb_load_sp(2); \
|
||||
break; \
|
||||
\
|
||||
case 0xAB: \
|
||||
/* ADD r3, sp, +imm */ \
|
||||
thumb_load_sp(3); \
|
||||
break; \
|
||||
\
|
||||
case 0xAC: \
|
||||
/* ADD r4, sp, +imm */ \
|
||||
thumb_load_sp(4); \
|
||||
break; \
|
||||
\
|
||||
case 0xAD: \
|
||||
/* ADD r5, sp, +imm */ \
|
||||
thumb_load_sp(5); \
|
||||
break; \
|
||||
\
|
||||
case 0xAE: \
|
||||
/* ADD r6, sp, +imm */ \
|
||||
thumb_load_sp(6); \
|
||||
break; \
|
||||
\
|
||||
case 0xAF: \
|
||||
/* ADD r7, sp, +imm */ \
|
||||
thumb_load_sp(7); \
|
||||
break; \
|
||||
/* ADD r0..7, sp, +imm */ \
|
||||
case 0xA8: thumb_load_sp(0); break; \
|
||||
case 0xA9: thumb_load_sp(1); break; \
|
||||
case 0xAA: thumb_load_sp(2); break; \
|
||||
case 0xAB: thumb_load_sp(3); break; \
|
||||
case 0xAC: thumb_load_sp(4); break; \
|
||||
case 0xAD: thumb_load_sp(5); break; \
|
||||
case 0xAE: thumb_load_sp(6); break; \
|
||||
case 0xAF: thumb_load_sp(7); break; \
|
||||
\
|
||||
case 0xB0 ... 0xB3: \
|
||||
if((opcode >> 7) & 0x01) \
|
||||
|
|
|
|||
|
|
@ -872,7 +872,6 @@ bool retro_load_game(const struct retro_game_info* info)
|
|||
strcpy(filename_bios, main_path);
|
||||
|
||||
bool bios_loaded = false;
|
||||
printf("USE %d\n", (int)selected_bios);
|
||||
if (selected_bios == auto_detect || selected_bios == official_bios)
|
||||
{
|
||||
bios_loaded = true;
|
||||
|
|
|
|||
|
|
@ -535,14 +535,14 @@ u32 arm_to_mips_reg[] =
|
|||
|
||||
#define generate_load_pc(ireg, new_pc) \
|
||||
{ \
|
||||
s32 pc_delta = new_pc - stored_pc; \
|
||||
s32 pc_delta = (new_pc) - (stored_pc); \
|
||||
if((pc_delta >= -32768) && (pc_delta <= 32767)) \
|
||||
{ \
|
||||
mips_emit_addiu(ireg, reg_pc, pc_delta); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
generate_load_imm(ireg, new_pc); \
|
||||
generate_load_imm(ireg, (new_pc)); \
|
||||
} \
|
||||
} \
|
||||
|
||||
|
|
@ -1697,6 +1697,9 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 store_mask, u32 address)
|
|||
arm_psr_##transfer_type(op_type, psr_reg); \
|
||||
} \
|
||||
|
||||
#define thumb_load_pc_pool_const(rd, value) \
|
||||
generate_load_imm(arm_to_mips_reg[rd], (value)); \
|
||||
|
||||
#define arm_access_memory_load(mem_type) \
|
||||
cycle_count += 2; \
|
||||
mips_emit_jal(mips_absolute_offset(execute_load_##mem_type)); \
|
||||
|
|
|
|||
|
|
@ -325,7 +325,7 @@ typedef enum
|
|||
x86_emit_mov_reg_mem(reg_##ireg, reg_base, reg_index * 4); \
|
||||
|
||||
#define generate_load_pc(ireg, new_pc) \
|
||||
x86_emit_mov_reg_imm(reg_##ireg, new_pc) \
|
||||
x86_emit_mov_reg_imm(reg_##ireg, (new_pc)) \
|
||||
|
||||
#define generate_load_imm(ireg, imm) \
|
||||
x86_emit_mov_reg_imm(reg_##ireg, imm) \
|
||||
|
|
@ -1894,6 +1894,10 @@ u32 function_cc execute_ror_imm_op(u32 value, u32 shift)
|
|||
|
||||
// Operation types: imm, mem_reg, mem_imm
|
||||
|
||||
#define thumb_load_pc_pool_const(reg_rd, value) \
|
||||
generate_load_pc(a0, (value)); \
|
||||
generate_store_reg(a0, reg_rd)
|
||||
|
||||
#define thumb_access_memory_load(mem_type, reg_rd) \
|
||||
cycle_count += 2; \
|
||||
generate_function_call(execute_load_##mem_type); \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue