swizzle address with pre-swapped data instead of endian-swap
This commit is contained in:
parent
b1cf0addb1
commit
35711d50e0
Binary file not shown.
|
@ -5,5 +5,5 @@
|
||||||
.data
|
.data
|
||||||
_open_gba_bios_rom:
|
_open_gba_bios_rom:
|
||||||
open_gba_bios_rom:
|
open_gba_bios_rom:
|
||||||
.incbin "bios/open_gba_bios.bin"
|
.incbin "bios/open_gba_bios.bigendian"
|
||||||
|
|
||||||
|
|
14
common.h
14
common.h
|
@ -137,15 +137,21 @@ typedef u32 fixed8_24;
|
||||||
|
|
||||||
#define eswap8(value) (value)
|
#define eswap8(value) (value)
|
||||||
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
||||||
#define eswap16(value) __builtin_bswap16(value)
|
// #define eswap16(value) __builtin_bswap16(value)
|
||||||
#define eswap32(value) __builtin_bswap32(value)
|
// #define eswap32(value) __builtin_bswap32(value)
|
||||||
|
#define eswap16(value) (value)
|
||||||
|
#define eswap32(value) (value)
|
||||||
|
#define swizzle_h(ofs) ((ofs) ^ 2)
|
||||||
|
#define swizzle_b(ofs) ((ofs) ^ 3)
|
||||||
#else
|
#else
|
||||||
#define eswap16(value) (value)
|
#define eswap16(value) (value)
|
||||||
#define eswap32(value) (value)
|
#define eswap32(value) (value)
|
||||||
|
#define swizzle_h(ofs) (ofs)
|
||||||
|
#define swizzle_b(ofs) (ofs)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define readaddress8(base, offset) eswap8( address8( base, offset))
|
#define readaddress8(base, offset) eswap8(address8( base, swizzle_b(offset)))
|
||||||
#define readaddress16(base, offset) eswap16(address16(base, offset))
|
#define readaddress16(base, offset) eswap16(address16(base, swizzle_h(offset)))
|
||||||
#define readaddress32(base, offset) eswap32(address32(base, offset))
|
#define readaddress32(base, offset) eswap32(address32(base, offset))
|
||||||
|
|
||||||
#define read_ioreg(regnum) (eswap16(io_registers[(regnum)]))
|
#define read_ioreg(regnum) (eswap16(io_registers[(regnum)]))
|
||||||
|
|
|
@ -2027,6 +2027,9 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
|
||||||
|
|
||||||
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
||||||
|
|
||||||
|
#define emit_swizzle_h(r) mips_emit_xori(r, r, 2)
|
||||||
|
#define emit_swizzle_b(r) mips_emit_xori(r, r, 3)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
400230: 00042e00 sll a1,a0,0x18
|
400230: 00042e00 sll a1,a0,0x18
|
||||||
400234: 00041602 srl v0,a0,0x18
|
400234: 00041602 srl v0,a0,0x18
|
||||||
|
@ -2076,6 +2079,9 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
|
#define emit_swizzle_h()
|
||||||
|
#define emit_swizzle_b()
|
||||||
|
|
||||||
#define emit_eswap32(r)
|
#define emit_eswap32(r)
|
||||||
#define emit_eswap16(r, sext)
|
#define emit_eswap16(r, sext)
|
||||||
|
|
||||||
|
@ -2115,22 +2121,24 @@ static void emit_mem_access_loadop(
|
||||||
switch (size) {
|
switch (size) {
|
||||||
case 2:
|
case 2:
|
||||||
mips_emit_lw(reg_rv, reg_rv, (base_addr & 0xffff));
|
mips_emit_lw(reg_rv, reg_rv, (base_addr & 0xffff));
|
||||||
emit_eswap32(reg_rv);
|
|
||||||
break;
|
break;
|
||||||
case 1:
|
case 1:
|
||||||
if (signext) {
|
if (signext) {
|
||||||
if (alignment) {
|
if (alignment) {
|
||||||
// Unaligned signed 16b load, is just a load byte (due to sign extension)
|
// Unaligned signed 16b load, is just a load byte (due to sign extension)
|
||||||
|
emit_swizzle_b(reg_rv);
|
||||||
mips_emit_lb(reg_rv, reg_rv, ((base_addr | 1) & 0xffff));
|
mips_emit_lb(reg_rv, reg_rv, ((base_addr | 1) & 0xffff));
|
||||||
} else {
|
} else {
|
||||||
|
emit_swizzle_h(reg_rv);
|
||||||
mips_emit_lh(reg_rv, reg_rv, (base_addr & 0xffff));
|
mips_emit_lh(reg_rv, reg_rv, (base_addr & 0xffff));
|
||||||
}
|
}
|
||||||
} else {
|
} else {
|
||||||
|
emit_swizzle_h(reg_rv);
|
||||||
mips_emit_lhu(reg_rv, reg_rv, (base_addr & 0xffff));
|
mips_emit_lhu(reg_rv, reg_rv, (base_addr & 0xffff));
|
||||||
}
|
}
|
||||||
emit_eswap16(reg_rv, signext);
|
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
|
emit_swizzle_b(reg_rv);
|
||||||
if (signext) {
|
if (signext) {
|
||||||
mips_emit_lb(reg_rv, reg_rv, (base_addr & 0xffff));
|
mips_emit_lb(reg_rv, reg_rv, (base_addr & 0xffff));
|
||||||
} else {
|
} else {
|
||||||
|
@ -2392,8 +2400,10 @@ static void emit_pmemst_stub(
|
||||||
if (realsize == 2) {
|
if (realsize == 2) {
|
||||||
mips_emit_lw(reg_temp, reg_temp, base_addr);
|
mips_emit_lw(reg_temp, reg_temp, base_addr);
|
||||||
} else if (realsize == 1) {
|
} else if (realsize == 1) {
|
||||||
|
emit_swizzle_h(reg_temp);
|
||||||
mips_emit_lh(reg_temp, reg_temp, base_addr);
|
mips_emit_lh(reg_temp, reg_temp, base_addr);
|
||||||
} else {
|
} else {
|
||||||
|
emit_swizzle_b(reg_temp);
|
||||||
mips_emit_lb(reg_temp, reg_temp, base_addr);
|
mips_emit_lb(reg_temp, reg_temp, base_addr);
|
||||||
}
|
}
|
||||||
// If the data is non zero, we just wrote over code
|
// If the data is non zero, we just wrote over code
|
||||||
|
@ -2403,12 +2413,12 @@ static void emit_pmemst_stub(
|
||||||
|
|
||||||
// Store the data (delay slot from the SMC branch)
|
// Store the data (delay slot from the SMC branch)
|
||||||
if (realsize == 2) {
|
if (realsize == 2) {
|
||||||
emit_eswap32(reg_a1);
|
|
||||||
mips_emit_sw(reg_a1, reg_rv, base_addr);
|
mips_emit_sw(reg_a1, reg_rv, base_addr);
|
||||||
} else if (realsize == 1) {
|
} else if (realsize == 1) {
|
||||||
emit_eswap16(reg_a1, false);
|
emit_swizzle_h(reg_rv);
|
||||||
mips_emit_sh(reg_a1, reg_rv, base_addr);
|
mips_emit_sh(reg_a1, reg_rv, base_addr);
|
||||||
} else {
|
} else {
|
||||||
|
emit_swizzle_b(reg_rv);
|
||||||
mips_emit_sb(reg_a1, reg_rv, base_addr);
|
mips_emit_sb(reg_a1, reg_rv, base_addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -2488,7 +2498,9 @@ static void emit_palette_hdl(
|
||||||
if (realsize == 2) {
|
if (realsize == 2) {
|
||||||
mips_emit_sw(reg_a1, reg_rv, 0x100);
|
mips_emit_sw(reg_a1, reg_rv, 0x100);
|
||||||
} else if (realsize == 1) {
|
} else if (realsize == 1) {
|
||||||
|
emit_swizzle_h(reg_rv);
|
||||||
mips_emit_sh(reg_a1, reg_rv, 0x100);
|
mips_emit_sh(reg_a1, reg_rv, 0x100);
|
||||||
|
emit_swizzle_h(reg_rv); // TODO: ???
|
||||||
}
|
}
|
||||||
|
|
||||||
// Convert and store in mirror memory
|
// Convert and store in mirror memory
|
||||||
|
|
Loading…
Reference in New Issue