Rework patch handlers (MIPS)
This commit is contained in:
David Guillen Fandos
parent
a160b6de50
commit
34b90277bc
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@ -58,8 +58,6 @@ u32 execute_lsr_flags_reg(u32 value, u32 shift);
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u32 execute_asr_flags_reg(u32 value, u32 shift);
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u32 execute_ror_flags_reg(u32 value, u32 shift);
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void reg_check();
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typedef enum
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{
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mips_reg_zero,
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@ -2581,6 +2579,7 @@ u8 swi_hle_handle[256] =
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// Pointer table to stubs, indexed by type and region
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extern u32 tmemld[11][16];
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extern u32 tmemst[ 4][16];
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extern u32 thnjal[15*16];
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void mips_lookup_pc();
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void smc_write();
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cpu_alert_type write_io_register8 (u32 address, u32 value);
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@ -3183,14 +3182,14 @@ static void emit_phand(
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mips_emit_srl(reg_temp, reg_a0, 24);
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#ifdef PSP
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mips_emit_addiu(reg_rv, reg_zero, 15*4); // Table limit (max)
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mips_emit_sll(reg_temp, reg_temp, 2); // Table is word indexed
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mips_emit_min(reg_temp, reg_temp, reg_rv);// Do not overflow table
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mips_emit_addiu(reg_rv, reg_zero, 15*4); // Table limit (max)
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mips_emit_sll(reg_temp, reg_temp, 2); // Table is word indexed
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mips_emit_min(reg_temp, reg_temp, reg_rv);// Do not overflow table
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#else
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mips_emit_sltiu(reg_rv, reg_temp, 0x0F); // Check for addr 0x1XXX.. 0xFXXX
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mips_emit_b(bne, reg_zero, reg_rv, 2); // Skip two insts (well, cant skip ds)
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mips_emit_sll(reg_temp, reg_temp, 2); // Table is word indexed
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mips_emit_addiu(reg_temp, reg_zero, 15*4);// Simulate ld/st to 0x0FXXX (open/ignore)
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mips_emit_sltiu(reg_rv, reg_temp, 0x0F); // Check for addr 0x1XXX.. 0xFXXX
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mips_emit_b(bne, reg_zero, reg_rv, 2); // Skip two insts (well, cant skip ds)
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mips_emit_sll(reg_temp, reg_temp, 2); // Table is word indexed
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mips_emit_addiu(reg_temp, reg_zero, 15*4);// Simulate ld/st to 0x0FXXX (open/ignore)
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#endif
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// Stores or byte-accesses do not care about alignment
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@ -3200,23 +3199,23 @@ static void emit_phand(
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}
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unsigned tbloff = 256 + 3*1024 + 220 + 4 * toff; // Skip regs and RAMs
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mips_emit_addu(reg_rv, reg_temp, reg_base); // Add to the base_reg the table offset
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mips_emit_lw(reg_rv, reg_rv, tbloff); // Read addr from table
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mips_emit_sll(reg_temp, reg_rv, 4); // 26 bit immediate to the MSB
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mips_emit_ori(reg_temp, reg_temp, 0x3); // JAL opcode
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mips_emit_rotr(reg_temp, reg_temp, 6); // Swap opcode and immediate
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mips_emit_sw(reg_temp, mips_reg_ra, -8); // Patch instruction!
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unsigned tbloff2 = tbloff + 960; // JAL opcode table
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mips_emit_addu(reg_temp, reg_temp, reg_base); // Add to the base_reg the table offset
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mips_emit_lw(reg_rv, reg_temp, tbloff); // Get func addr from 1st table
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mips_emit_lw(reg_temp, reg_temp, tbloff2); // Get opcode from 2nd table
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mips_emit_sw(reg_temp, mips_reg_ra, -8); // Patch instruction!
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#ifdef PSP
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mips_emit_cache(0x1A, mips_reg_ra, -8);
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mips_emit_jr(reg_rv); // Jump directly to target for speed
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mips_emit_cache(0x08, mips_reg_ra, -8);
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mips_emit_cache(0x1A, mips_reg_ra, -8);
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mips_emit_jr(reg_rv); // Jump directly to target for speed
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mips_emit_cache(0x08, mips_reg_ra, -8);
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#else
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mips_emit_jr(reg_rv);
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mips_emit_synci(mips_reg_ra, -8);
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mips_emit_jr(reg_rv);
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mips_emit_synci(mips_reg_ra, -8);
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#endif
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// Round up handlers to 16 instructions for easy addressing :)
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// Round up handlers to 16 instructions for easy addressing
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// PSP/MIPS32r2 uses up to 12 insts
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while (translation_ptr - *tr_ptr < 64) {
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mips_emit_nop();
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}
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@ -3329,6 +3328,11 @@ void init_emitter() {
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handler(2, &stinfo[i], 2, false, &translation_ptr); // st u32
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handler(3, &stinfo[i], 2, true, &translation_ptr); // st aligned 32
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}
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// Generate JAL tables
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u32 *tmemptr = &tmemld[0][0];
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for (i = 0; i < 15*16; i++)
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thnjal[i] = ((tmemptr[i] >> 2) & 0x3FFFFFF) | (mips_opcode_jal << 26);
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}
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u32 execute_arm_translate_internal(u32 cycles, void *regptr);
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@ -35,12 +35,9 @@
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.global execute_lsr_flags_reg
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.global execute_asr_flags_reg
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.global execute_arm_translate_internal
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.global icache_region_sync
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.global reg_check
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.global palette_ram
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.global palette_ram_converted
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.global oam_ram
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.global init_emitter
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.global mips_lookup_pc
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.global smc_write
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.global mips_cheat_hook
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@ -49,7 +46,7 @@
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.global memory_map_read
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.global tmemld
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.global tmemst
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.global tmemst
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.global thnjal
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.global reg
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.global spsr
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.global reg_mode
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@ -126,7 +123,7 @@
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.equ SUPERVISOR_SPSR, (3 * 4 + SPSR_BASE)
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.equ SUPERVISOR_LR, ((3 * (7 * 4)) + (6 * 4) + REGMODE_BASE)
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.equ FNPTRS_MEMOPS, (REGMODE_BASE + 196)
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.equ FNPTRS_BASE, (FNPTRS_MEMOPS + 960)
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.equ FNPTRS_BASE, (FNPTRS_MEMOPS + 960*2)
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.set noat
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.set noreorder
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@ -640,6 +637,8 @@ tmemld:
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.space 704
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tmemst:
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.space 256
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thnjal:
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.space 960
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fnptrs:
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.long update_gba # 0
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.long block_lookup_address_arm # 1
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