minor cleanup and write an emit for load/store doubleword
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parent
9a4ee26edc
commit
2e9fb813a9
2
Makefile
2
Makefile
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@ -444,7 +444,7 @@ else ifeq ($(platform), n64)
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CFLAGS += -march=vr4300 -mtune=vr4300 -falign-functions=32
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CFLAGS += -march=vr4300 -mtune=vr4300 -falign-functions=32
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CFLAGS += -DN64 -DUSE_RGBA5551_FORMAT -DSMALL_TRANSLATION_CACHE -DROM_BUFFER_SIZE=1
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CFLAGS += -DN64 -DUSE_RGBA5551_FORMAT -DSMALL_TRANSLATION_CACHE -DROM_BUFFER_SIZE=1
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CFLAGS += -I$(N64_INST)/include/
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CFLAGS += -I$(N64_INST)/include/
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HAVE_DYNAREC = 1
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HAVE_DYNAREC := 1
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CPU_ARCH := mips
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CPU_ARCH := mips
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STATIC_LINKING = 1
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STATIC_LINKING = 1
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FRONTEND_SUPPORTS_RGB565 = 0
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FRONTEND_SUPPORTS_RGB565 = 0
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2
cheats.c
2
cheats.c
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@ -118,6 +118,8 @@ static void process_cheat_codebreaker(cheat_type *cheat, u16 pad)
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case 4 ... 5:
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case 4 ... 5:
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bvalue = cheat->codes[i].value >> (40 - off*8);
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bvalue = cheat->codes[i].value >> (40 - off*8);
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break;
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break;
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default:
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continue;
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};
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};
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write_memory8(address, bvalue);
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write_memory8(address, bvalue);
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address++;
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address++;
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@ -150,6 +150,8 @@ typedef enum
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mips_opcode_sh = 0x29,
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mips_opcode_sh = 0x29,
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mips_opcode_sw = 0x2B,
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mips_opcode_sw = 0x2B,
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mips_opcode_cache = 0x2F,
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mips_opcode_cache = 0x2F,
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mips_opcode_ld = 0x37,
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mips_opcode_sd = 0x3F,
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} mips_opcode;
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} mips_opcode;
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#ifdef NINTENDO64
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#ifdef NINTENDO64
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@ -336,6 +338,9 @@ typedef enum
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#define mips_emit_lw(rt, rs, offset) \
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#define mips_emit_lw(rt, rs, offset) \
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mips_emit_imm(lw, rs, rt, offset) \
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mips_emit_imm(lw, rs, rt, offset) \
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#define mips_emit_ld(rt, rs, offset) \
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mips_emit_imm(ld, rs, rt, offset) \
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#define mips_emit_sb(rt, rs, offset) \
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#define mips_emit_sb(rt, rs, offset) \
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mips_emit_imm(sb, rs, rt, offset) \
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mips_emit_imm(sb, rs, rt, offset) \
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@ -345,6 +350,9 @@ typedef enum
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#define mips_emit_sw(rt, rs, offset) \
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#define mips_emit_sw(rt, rs, offset) \
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mips_emit_imm(sw, rs, rt, offset) \
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mips_emit_imm(sw, rs, rt, offset) \
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#define mips_emit_sd(rt, rs, offset) \
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mips_emit_imm(sd, rs, rt, offset) \
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#define mips_emit_lui(rt, imm) \
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#define mips_emit_lui(rt, imm) \
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mips_emit_imm(lui, 0, rt, imm) \
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mips_emit_imm(lui, 0, rt, imm) \
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