184 lines
8.9 KiB
C
184 lines
8.9 KiB
C
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/* gameplaySP
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*
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* Copyright (C) 2006 Exophase <exophase@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define arm_decode_data_proc_reg() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_data_proc_imm() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 imm; \
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ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \
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#define arm_decode_psr_reg() \
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u32 psr_field = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_psr_imm() \
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u32 psr_field = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 imm; \
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ror(imm, opcode & 0xFF, ((opcode >> 8) & 0x0F) * 2) \
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#define arm_decode_branchx() \
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u32 rn = opcode & 0x0F \
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#define arm_decode_multiply() \
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u32 rd = (opcode >> 16) & 0x0F; \
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u32 rn = (opcode >> 12) & 0x0F; \
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u32 rs = (opcode >> 8) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_multiply_long() \
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u32 rdhi = (opcode >> 16) & 0x0F; \
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u32 rdlo = (opcode >> 12) & 0x0F; \
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u32 rn = (opcode >> 8) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_swap() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_half_trans_r() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_half_trans_of() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F) \
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#define arm_decode_data_trans_imm() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 offset = opcode & 0x0FFF \
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#define arm_decode_data_trans_reg() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 rd = (opcode >> 12) & 0x0F; \
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u32 rm = opcode & 0x0F \
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#define arm_decode_block_trans() \
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u32 rn = (opcode >> 16) & 0x0F; \
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u32 reg_list = opcode & 0xFFFF \
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#define arm_decode_branch() \
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s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \
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#define thumb_decode_shift() \
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u32 imm = (opcode >> 6) & 0x1F; \
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u32 rs = (opcode >> 3) & 0x07; \
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u32 rd = opcode & 0x07 \
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#define thumb_decode_add_sub() \
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u32 rn = (opcode >> 6) & 0x07; \
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u32 rs = (opcode >> 3) & 0x07; \
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u32 rd = opcode & 0x07 \
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#define thumb_decode_add_sub_imm() \
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u32 imm = (opcode >> 6) & 0x07; \
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u32 rs = (opcode >> 3) & 0x07; \
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u32 rd = opcode & 0x07 \
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#define thumb_decode_imm() \
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u32 imm = opcode & 0xFF \
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#define thumb_decode_alu_op() \
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u32 rs = (opcode >> 3) & 0x07; \
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u32 rd = opcode & 0x07 \
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#define thumb_decode_hireg_op() \
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u32 rs = (opcode >> 3) & 0x0F; \
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u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07) \
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#define thumb_decode_mem_reg() \
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u32 ro = (opcode >> 6) & 0x07; \
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u32 rb = (opcode >> 3) & 0x07; \
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u32 rd = opcode & 0x07 \
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#define thumb_decode_mem_imm() \
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u32 imm = (opcode >> 6) & 0x1F; \
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u32 rb = (opcode >> 3) & 0x07; \
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u32 rd = opcode & 0x07 \
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#define thumb_decode_add_sp() \
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u32 imm = opcode & 0x7F \
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#define thumb_decode_rlist() \
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u32 reg_list = opcode & 0xFF \
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#define thumb_decode_branch_cond() \
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s32 offset = (s8)(opcode & 0xFF) \
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#define thumb_decode_swi() \
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u32 comment = opcode & 0xFF \
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#define thumb_decode_branch() \
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u32 offset = opcode & 0x07FF \
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const char *condition_table[] =
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{
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"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
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"hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
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};
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const char *data_proc_opcode_table[] =
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{
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"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc",
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"tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn"
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};
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u32 print_disasm_arm_instruction(u32 opcode)
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{
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u32 condition = opcode >> 28;
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switch((opcode >> 25) & 0x07)
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{
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// Data processing reg, multiply, bx, memory transfer half/byte, swap,
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// PSR reg
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case 0x0:
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// Data processing imm, PSR imm
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case 0x1:
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// Memory transfer imm
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case 0x2:
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// Memory transfer reg, undefined
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case 0x3:
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// Block memory transfer
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case 0x4:
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// Branch
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case 0x5:
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// Coprocessor
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case 0x6:
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// Coprocessor, SWI
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case 0x7:
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}
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