diff --git a/cpu_threaded.c b/cpu_threaded.c index d15b5af..6f52b8f 100644 --- a/cpu_threaded.c +++ b/cpu_threaded.c @@ -286,7 +286,7 @@ void translate_icache_sync() { check_pc_region(pc); \ opcode = readaddress32(pc_address_block, (pc & 0x7FFF)); \ condition = block_data[block_data_position].condition; \ - \ + printf("%x: %08x ", pc, opcode); \ if((condition != last_condition) || (condition >= 0x20)) \ { \ if((last_condition & 0x0F) != 0x0E) \ @@ -312,19 +312,19 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn], -rm */ \ + printf("STRH rd, [rn], -rm\n"); \ arm_access_memory(store, down, post, u16, half_reg); \ } \ else \ { \ - /* MUL rd, rm, rs */ \ + printf("MUL rd, rm, rs\n"); \ arm_multiply(no, no); \ cycle_count += 2; /* variable 1..4, pick 2 as an aprox. */ \ } \ } \ else \ { \ - /* AND rd, rn, reg_op */ \ + printf("AND rd, rn, reg_op\n"); \ arm_data_proc(and, reg, no_flags); \ } \ break; \ @@ -335,30 +335,30 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 0: \ - /* MULS rd, rm, rs */ \ + printf("MULS rd, rm, rs\n"); \ arm_multiply(no, yes); \ cycle_count += 2; /* variable 1..4, pick 2 as an aprox. */ \ break; \ \ case 1: \ - /* LDRH rd, [rn], -rm */ \ + printf("LDRH rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], -rm */ \ + printf("LDRSB rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], -rm */ \ + printf("LDRSH rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* ANDS rd, rn, reg_op */ \ + printf("ANDS rd, rn, reg_op\n"); \ arm_data_proc(ands, reg_flags, flags); \ } \ break; \ @@ -368,19 +368,19 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn], -rm */ \ + printf("STRH rd, [rn], -rm\n"); \ arm_access_memory(store, down, post, u16, half_reg); \ } \ else \ { \ - /* MLA rd, rm, rs, rn */ \ + printf("MLA rd, rm, rs, rn\n"); \ arm_multiply(yes, no); \ cycle_count += 3; /* variable 2..5, pick 3 as an aprox. */ \ } \ } \ else \ { \ - /* EOR rd, rn, reg_op */ \ + printf("EOR rd, rn, reg_op\n"); \ arm_data_proc(eor, reg, no_flags); \ } \ break; \ @@ -391,30 +391,30 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 0: \ - /* MLAS rd, rm, rs, rn */ \ + printf("MLAS rd, rm, rs, rn\n"); \ arm_multiply(yes, yes); \ - cycle_count += 3; /* variable 2..5, pick 3 as an aprox. */ \ + cycle_count += 3; printf("variable 2..5, pick 3 as an aprox.\n"); \ break; \ \ case 1: \ - /* LDRH rd, [rn], -rm */ \ + printf("LDRH rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], -rm */ \ + printf("LDRSB rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], -rm */ \ + printf("LDRSH rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* EORS rd, rn, reg_op */ \ + printf("EORS rd, rn, reg_op\n"); \ arm_data_proc(eors, reg_flags, flags); \ } \ break; \ @@ -422,12 +422,12 @@ void translate_icache_sync() { case 0x04: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn], -imm */ \ + printf("STRH rd, [rn], -imm\n"); \ arm_access_memory(store, down, post, u16, half_imm); \ } \ else \ { \ - /* SUB rd, rn, reg_op */ \ + printf("SUB rd, rn, reg_op\n"); \ arm_data_proc(sub, reg, no_flags); \ } \ break; \ @@ -438,24 +438,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn], -imm */ \ + printf("LDRH rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], -imm */ \ + printf("LDRSB rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], -imm */ \ + printf("LDRSH rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* SUBS rd, rn, reg_op */ \ + printf("SUBS rd, rn, reg_op\n"); \ arm_data_proc(subs, reg, flags); \ } \ break; \ @@ -463,12 +463,12 @@ void translate_icache_sync() { case 0x06: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn], -imm */ \ + printf("STRH rd, [rn], -imm\n"); \ arm_access_memory(store, down, post, u16, half_imm); \ } \ else \ { \ - /* RSB rd, rn, reg_op */ \ + printf("RSB rd, rn, reg_op\n"); \ arm_data_proc(rsb, reg, no_flags); \ } \ break; \ @@ -479,24 +479,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn], -imm */ \ + printf("LDRH rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], -imm */ \ + printf("LDRSB rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], -imm */ \ + printf("LDRSH rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* RSBS rd, rn, reg_op */ \ + printf("RSBS rd, rn, reg_op\n"); \ arm_data_proc(rsbs, reg, flags); \ } \ break; \ @@ -506,19 +506,19 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn], +rm */ \ + printf("STRH rd, [rn], +rm\n"); \ arm_access_memory(store, up, post, u16, half_reg); \ } \ else \ { \ - /* UMULL rd, rm, rs */ \ + printf("UMULL rd, rm, rs\n"); \ arm_multiply_long(u64, no, no); \ cycle_count += 3; /* this is an aproximation :P */ \ } \ } \ else \ { \ - /* ADD rd, rn, reg_op */ \ + printf("ADD rd, rn, reg_op\n"); \ arm_data_proc(add, reg, no_flags); \ } \ break; \ @@ -529,30 +529,30 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 0: \ - /* UMULLS rdlo, rdhi, rm, rs */ \ + printf("UMULLS rdlo, rdhi, rm, rs\n"); \ arm_multiply_long(u64, no, yes); \ cycle_count += 3; /* this is an aproximation :P */ \ break; \ \ case 1: \ - /* LDRH rd, [rn], +rm */ \ + printf("LDRH rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], +rm */ \ + printf("LDRSB rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], +rm */ \ + printf("LDRSH rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* ADDS rd, rn, reg_op */ \ + printf("ADDS rd, rn, reg_op\n"); \ arm_data_proc(adds, reg, flags); \ } \ break; \ @@ -562,19 +562,19 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn], +rm */ \ + printf("STRH rd, [rn], +rm\n"); \ arm_access_memory(store, up, post, u16, half_reg); \ } \ else \ { \ - /* UMLAL rd, rm, rs */ \ + printf("UMLAL rd, rm, rs\n"); \ arm_multiply_long(u64_add, yes, no); \ cycle_count += 3; /* Between 2 and 5 cycles? */ \ } \ } \ else \ { \ - /* ADC rd, rn, reg_op */ \ + printf("ADC rd, rn, reg_op\n"); \ arm_data_proc(adc, reg, no_flags); \ } \ break; \ @@ -585,30 +585,30 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 0: \ - /* UMLALS rdlo, rdhi, rm, rs */ \ + printf("UMLALS rdlo, rdhi, rm, rs\n"); \ arm_multiply_long(u64_add, yes, yes); \ cycle_count += 3; /* Between 2 and 5 cycles? */ \ break; \ \ case 1: \ - /* LDRH rd, [rn], +rm */ \ + printf("LDRH rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], +rm */ \ + printf("LDRSB rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], +rm */ \ + printf("LDRSH rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* ADCS rd, rn, reg_op */ \ + printf("ADCS rd, rn, reg_op\n"); \ arm_data_proc(adcs, reg, flags); \ } \ break; \ @@ -618,19 +618,19 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn], +imm */ \ + printf("STRH rd, [rn], +imm\n"); \ arm_access_memory(store, up, post, u16, half_imm); \ } \ else \ { \ - /* SMULL rd, rm, rs */ \ + printf("SMULL rd, rm, rs\n"); \ arm_multiply_long(s64, no, no); \ cycle_count += 2; /* Between 1 and 4 cycles? */ \ } \ } \ else \ { \ - /* SBC rd, rn, reg_op */ \ + printf("SBC rd, rn, reg_op\n"); \ arm_data_proc(sbc, reg, no_flags); \ } \ break; \ @@ -641,30 +641,30 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 0: \ - /* SMULLS rdlo, rdhi, rm, rs */ \ + printf("SMULLS rdlo, rdhi, rm, rs\n"); \ arm_multiply_long(s64, no, yes); \ cycle_count += 2; /* Between 1 and 4 cycles? */ \ break; \ \ case 1: \ - /* LDRH rd, [rn], +imm */ \ + printf("LDRH rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], +imm */ \ + printf("LDRSB rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], +imm */ \ + printf("LDRSH rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* SBCS rd, rn, reg_op */ \ + printf("SBCS rd, rn, reg_op\n"); \ arm_data_proc(sbcs, reg, flags); \ } \ break; \ @@ -674,19 +674,19 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn], +imm */ \ + printf("STRH rd, [rn], +imm\n"); \ arm_access_memory(store, up, post, u16, half_imm); \ } \ else \ { \ - /* SMLAL rd, rm, rs */ \ + printf("SMLAL rd, rm, rs\n"); \ arm_multiply_long(s64_add, yes, no); \ cycle_count += 3; /* Between 2 and 5 cycles? */ \ } \ } \ else \ { \ - /* RSC rd, rn, reg_op */ \ + printf("RSC rd, rn, reg_op\n"); \ arm_data_proc(rsc, reg, no_flags); \ } \ break; \ @@ -697,30 +697,30 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 0: \ - /* SMLALS rdlo, rdhi, rm, rs */ \ + printf("SMLALS rdlo, rdhi, rm, rs\n"); \ arm_multiply_long(s64_add, yes, yes); \ cycle_count += 3; /* Between 2 and 5 cycles? */ \ break; \ \ case 1: \ - /* LDRH rd, [rn], +imm */ \ + printf("LDRH rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn], +imm */ \ + printf("LDRSB rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn], +imm */ \ + printf("LDRSH rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* RSCS rd, rn, reg_op */ \ + printf("RSCS rd, rn, reg_op\n"); \ arm_data_proc(rscs, reg, flags); \ } \ break; \ @@ -730,18 +730,18 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn - rm] */ \ + printf("STRH rd, [rn - rm]\n"); \ arm_access_memory(store, down, pre, u16, half_reg); \ } \ else \ { \ - /* SWP rd, rm, [rn] */ \ + printf("SWP rd, rm, [rn]\n"); \ arm_swap(u32); \ } \ } \ else \ { \ - /* MRS rd, cpsr */ \ + printf("MRS rd, cpsr\n"); \ arm_psr(reg, read, cpsr); \ } \ break; \ @@ -752,24 +752,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn - rm] */ \ + printf("LDRH rd, [rn - rm]\n"); \ arm_access_memory(load, down, pre, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn - rm] */ \ + printf("LDRSB rd, [rn - rm]\n"); \ arm_access_memory(load, down, pre, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn - rm] */ \ + printf("LDRSH rd, [rn - rm]\n"); \ arm_access_memory(load, down, pre, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* TST rd, rn, reg_op */ \ + printf("TST rd, rn, reg_op\n"); \ arm_data_proc_test(tst, reg_flags); \ } \ break; \ @@ -777,19 +777,19 @@ void translate_icache_sync() { case 0x12: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn - rm]! */ \ + printf("STRH rd, [rn - rm]!\n"); \ arm_access_memory(store, down, pre_wb, u16, half_reg); \ } \ else \ { \ if(opcode & 0x10) \ { \ - /* BX rn */ \ + printf("BX rn\n"); \ arm_bx(); \ } \ else \ { \ - /* MSR cpsr, rm */ \ + printf("MSR cpsr, rm\n"); \ arm_psr(reg, store, cpsr); \ } \ } \ @@ -801,24 +801,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn - rm]! */ \ + printf("LDRH rd, [rn - rm]!\n"); \ arm_access_memory(load, down, pre_wb, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn - rm]! */ \ + printf("LDRSB rd, [rn - rm]!\n"); \ arm_access_memory(load, down, pre_wb, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn - rm]! */ \ + printf("LDRSH rd, [rn - rm]!\n"); \ arm_access_memory(load, down, pre_wb, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* TEQ rd, rn, reg_op */ \ + printf("TEQ rd, rn, reg_op\n"); \ arm_data_proc_test(teq, reg_flags); \ } \ break; \ @@ -828,18 +828,18 @@ void translate_icache_sync() { { \ if(opcode & 0x20) \ { \ - /* STRH rd, [rn - imm] */ \ + printf("STRH rd, [rn - imm]\n"); \ arm_access_memory(store, down, pre, u16, half_imm); \ } \ else \ { \ - /* SWPB rd, rm, [rn] */ \ + printf("SWPB rd, rm, [rn]\n"); \ arm_swap(u8); \ } \ } \ else \ { \ - /* MRS rd, spsr */ \ + printf("MRS rd, spsr\n"); \ arm_psr(reg, read, spsr); \ } \ break; \ @@ -850,24 +850,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn - imm] */ \ + printf("LDRH rd, [rn - imm]\n"); \ arm_access_memory(load, down, pre, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn - imm] */ \ + printf("LDRSB rd, [rn - imm]\n"); \ arm_access_memory(load, down, pre, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn - imm] */ \ + printf("LDRSH rd, [rn - imm]\n"); \ arm_access_memory(load, down, pre, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* CMP rn, reg_op */ \ + printf("CMP rn, reg_op\n"); \ arm_data_proc_test(cmp, reg); \ } \ break; \ @@ -875,12 +875,12 @@ void translate_icache_sync() { case 0x16: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn - imm]! */ \ + printf("STRH rd, [rn - imm]!\n"); \ arm_access_memory(store, down, pre_wb, u16, half_imm); \ } \ else \ { \ - /* MSR spsr, rm */ \ + printf("MSR spsr, rm\n"); \ arm_psr(reg, store, spsr); \ } \ break; \ @@ -891,24 +891,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn - imm]! */ \ + printf("LDRH rd, [rn - imm]!\n"); \ arm_access_memory(load, down, pre_wb, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn - imm]! */ \ + printf("LDRSB rd, [rn - imm]!\n"); \ arm_access_memory(load, down, pre_wb, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn - imm]! */ \ + printf("LDRSH rd, [rn - imm]!\n"); \ arm_access_memory(load, down, pre_wb, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* CMN rd, rn, reg_op */ \ + printf("CMN rd, rn, reg_op\n"); \ arm_data_proc_test(cmn, reg); \ } \ break; \ @@ -916,12 +916,12 @@ void translate_icache_sync() { case 0x18: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn + rm] */ \ + printf("STRH rd, [rn + rm]\n"); \ arm_access_memory(store, up, pre, u16, half_reg); \ } \ else \ { \ - /* ORR rd, rn, reg_op */ \ + printf("ORR rd, rn, reg_op\n"); \ arm_data_proc(orr, reg, no_flags); \ } \ break; \ @@ -932,24 +932,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn + rm] */ \ + printf("LDRH rd, [rn + rm]\n"); \ arm_access_memory(load, up, pre, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn + rm] */ \ + printf("LDRSB rd, [rn + rm]\n"); \ arm_access_memory(load, up, pre, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn + rm] */ \ + printf("LDRSH rd, [rn + rm]\n"); \ arm_access_memory(load, up, pre, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* ORRS rd, rn, reg_op */ \ + printf("ORRS rd, rn, reg_op\n"); \ arm_data_proc(orrs, reg_flags, flags); \ } \ break; \ @@ -957,12 +957,12 @@ void translate_icache_sync() { case 0x1A: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn + rm]! */ \ + printf("STRH rd, [rn + rm]!\n"); \ arm_access_memory(store, up, pre_wb, u16, half_reg); \ } \ else \ { \ - /* MOV rd, reg_op */ \ + printf("MOV rd, reg_op\n"); \ arm_data_proc_unary(mov, reg, no_flags); \ } \ break; \ @@ -973,24 +973,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn + rm]! */ \ + printf("LDRH rd, [rn + rm]!\n"); \ arm_access_memory(load, up, pre_wb, u16, half_reg); \ break; \ \ case 2: \ - /* LDRSB rd, [rn + rm]! */ \ + printf("LDRSB rd, [rn + rm]!\n"); \ arm_access_memory(load, up, pre_wb, s8, half_reg); \ break; \ \ case 3: \ - /* LDRSH rd, [rn + rm]! */ \ + printf("LDRSH rd, [rn + rm]!\n"); \ arm_access_memory(load, up, pre_wb, s16, half_reg); \ break; \ } \ } \ else \ { \ - /* MOVS rd, reg_op */ \ + printf("MOVS rd, reg_op\n"); \ arm_data_proc_unary(movs, reg_flags, flags); \ } \ break; \ @@ -998,12 +998,12 @@ void translate_icache_sync() { case 0x1C: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn + imm] */ \ + printf("STRH rd, [rn + imm]\n"); \ arm_access_memory(store, up, pre, u16, half_imm); \ } \ else \ { \ - /* BIC rd, rn, reg_op */ \ + printf("BIC rd, rn, reg_op\n"); \ arm_data_proc(bic, reg, no_flags); \ } \ break; \ @@ -1014,24 +1014,24 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn + imm] */ \ + printf("LDRH rd, [rn + imm]\n"); \ arm_access_memory(load, up, pre, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn + imm] */ \ + printf("LDRSB rd, [rn + imm]\n"); \ arm_access_memory(load, up, pre, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn + imm] */ \ + printf("LDRSH rd, [rn + imm]\n"); \ arm_access_memory(load, up, pre, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* BICS rd, rn, reg_op */ \ + printf("BICS rd, rn, reg_op\n"); \ arm_data_proc(bics, reg_flags, flags); \ } \ break; \ @@ -1039,12 +1039,12 @@ void translate_icache_sync() { case 0x1E: \ if((opcode & 0x90) == 0x90) \ { \ - /* STRH rd, [rn + imm]! */ \ + printf("STRH rd, [rn + imm]!\n"); \ arm_access_memory(store, up, pre_wb, u16, half_imm); \ } \ else \ { \ - /* MVN rd, reg_op */ \ + printf("MVN rd, reg_op\n"); \ arm_data_proc_unary(mvn, reg, no_flags); \ } \ break; \ @@ -1055,668 +1055,668 @@ void translate_icache_sync() { switch((opcode >> 5) & 0x03) \ { \ case 1: \ - /* LDRH rd, [rn + imm]! */ \ + printf("LDRH rd, [rn + imm]!\n"); \ arm_access_memory(load, up, pre_wb, u16, half_imm); \ break; \ \ case 2: \ - /* LDRSB rd, [rn + imm]! */ \ + printf("LDRSB rd, [rn + imm]!\n"); \ arm_access_memory(load, up, pre_wb, s8, half_imm); \ break; \ \ case 3: \ - /* LDRSH rd, [rn + imm]! */ \ + printf("LDRSH rd, [rn + imm]!\n"); \ arm_access_memory(load, up, pre_wb, s16, half_imm); \ break; \ } \ } \ else \ { \ - /* MVNS rd, rn, reg_op */ \ + printf("MVNS rd, rn, reg_op\n"); \ arm_data_proc_unary(mvns, reg_flags, flags); \ } \ break; \ \ case 0x20: \ - /* AND rd, rn, imm */ \ + printf("AND rd, rn, imm\n"); \ arm_data_proc(and, imm, no_flags); \ break; \ \ case 0x21: \ - /* ANDS rd, rn, imm */ \ + printf("ANDS rd, rn, imm\n"); \ arm_data_proc(ands, imm_flags, flags); \ break; \ \ case 0x22: \ - /* EOR rd, rn, imm */ \ + printf("EOR rd, rn, imm\n"); \ arm_data_proc(eor, imm, no_flags); \ break; \ \ case 0x23: \ - /* EORS rd, rn, imm */ \ + printf("EORS rd, rn, imm\n"); \ arm_data_proc(eors, imm_flags, flags); \ break; \ \ case 0x24: \ - /* SUB rd, rn, imm */ \ + printf("SUB rd, rn, imm\n"); \ arm_data_proc(sub, imm, no_flags); \ break; \ \ case 0x25: \ - /* SUBS rd, rn, imm */ \ + printf("SUBS rd, rn, imm\n"); \ arm_data_proc(subs, imm, flags); \ break; \ \ case 0x26: \ - /* RSB rd, rn, imm */ \ + printf("RSB rd, rn, imm\n"); \ arm_data_proc(rsb, imm, no_flags); \ break; \ \ case 0x27: \ - /* RSBS rd, rn, imm */ \ + printf("RSBS rd, rn, imm\n"); \ arm_data_proc(rsbs, imm, flags); \ break; \ \ case 0x28: \ - /* ADD rd, rn, imm */ \ + printf("ADD rd, rn, imm\n"); \ arm_data_proc(add, imm, no_flags); \ break; \ \ case 0x29: \ - /* ADDS rd, rn, imm */ \ + printf("ADDS rd, rn, imm\n"); \ arm_data_proc(adds, imm, flags); \ break; \ \ case 0x2A: \ - /* ADC rd, rn, imm */ \ + printf("ADC rd, rn, imm\n"); \ arm_data_proc(adc, imm, no_flags); \ break; \ \ case 0x2B: \ - /* ADCS rd, rn, imm */ \ + printf("ADCS rd, rn, imm\n"); \ arm_data_proc(adcs, imm, flags); \ break; \ \ case 0x2C: \ - /* SBC rd, rn, imm */ \ + printf("SBC rd, rn, imm\n"); \ arm_data_proc(sbc, imm, no_flags); \ break; \ \ case 0x2D: \ - /* SBCS rd, rn, imm */ \ + printf("SBCS rd, rn, imm\n"); \ arm_data_proc(sbcs, imm, flags); \ break; \ \ case 0x2E: \ - /* RSC rd, rn, imm */ \ + printf("RSC rd, rn, imm\n"); \ arm_data_proc(rsc, imm, no_flags); \ break; \ \ case 0x2F: \ - /* RSCS rd, rn, imm */ \ + printf("RSCS rd, rn, imm\n"); \ arm_data_proc(rscs, imm, flags); \ break; \ \ case 0x30 ... 0x31: \ - /* TST rn, imm */ \ + printf("TST rn, imm\n"); \ arm_data_proc_test(tst, imm); \ break; \ \ case 0x32: \ - /* MSR cpsr, imm */ \ + printf("MSR cpsr, imm\n"); \ arm_psr(imm, store, cpsr); \ break; \ \ case 0x33: \ - /* TEQ rn, imm */ \ + printf("TEQ rn, imm\n"); \ arm_data_proc_test(teq, imm); \ break; \ \ case 0x34 ... 0x35: \ - /* CMP rn, imm */ \ + printf("CMP rn, imm\n"); \ arm_data_proc_test(cmp, imm); \ break; \ \ case 0x36: \ - /* MSR spsr, imm */ \ + printf("MSR spsr, imm\n"); \ arm_psr(imm, store, spsr); \ break; \ \ case 0x37: \ - /* CMN rn, imm */ \ + printf("CMN rn, imm\n"); \ arm_data_proc_test(cmn, imm); \ break; \ \ case 0x38: \ - /* ORR rd, rn, imm */ \ + printf("ORR rd, rn, imm\n"); \ arm_data_proc(orr, imm, no_flags); \ break; \ \ case 0x39: \ - /* ORRS rd, rn, imm */ \ + printf("ORRS rd, rn, imm\n"); \ arm_data_proc(orrs, imm_flags, flags); \ break; \ \ case 0x3A: \ - /* MOV rd, imm */ \ + printf("MOV rd, imm\n"); \ arm_data_proc_unary(mov, imm, no_flags); \ break; \ \ case 0x3B: \ - /* MOVS rd, imm */ \ + printf("MOVS rd, imm\n"); \ arm_data_proc_unary(movs, imm_flags, flags); \ break; \ \ case 0x3C: \ - /* BIC rd, rn, imm */ \ + printf("BIC rd, rn, imm\n"); \ arm_data_proc(bic, imm, no_flags); \ break; \ \ case 0x3D: \ - /* BICS rd, rn, imm */ \ + printf("BICS rd, rn, imm\n"); \ arm_data_proc(bics, imm_flags, flags); \ break; \ \ case 0x3E: \ - /* MVN rd, imm */ \ + printf("MVN rd, imm\n"); \ arm_data_proc_unary(mvn, imm, no_flags); \ break; \ \ case 0x3F: \ - /* MVNS rd, imm */ \ + printf("MVNS rd, imm\n"); \ arm_data_proc_unary(mvns, imm_flags, flags); \ break; \ \ case 0x40: \ - /* STR rd, [rn], -imm */ \ + printf("STR rd, [rn], -imm\n"); \ arm_access_memory(store, down, post, u32, imm); \ break; \ \ case 0x41: \ - /* LDR rd, [rn], -imm */ \ + printf("LDR rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, u32, imm); \ break; \ \ case 0x42: \ - /* STRT rd, [rn], -imm */ \ + printf("STRT rd, [rn], -imm\n"); \ arm_access_memory(store, down, post, u32, imm); \ break; \ \ case 0x43: \ - /* LDRT rd, [rn], -imm */ \ + printf("LDRT rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, u32, imm); \ break; \ \ case 0x44: \ - /* STRB rd, [rn], -imm */ \ + printf("STRB rd, [rn], -imm\n"); \ arm_access_memory(store, down, post, u8, imm); \ break; \ \ case 0x45: \ - /* LDRB rd, [rn], -imm */ \ + printf("LDRB rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, u8, imm); \ break; \ \ case 0x46: \ - /* STRBT rd, [rn], -imm */ \ + printf("STRBT rd, [rn], -imm\n"); \ arm_access_memory(store, down, post, u8, imm); \ break; \ \ case 0x47: \ - /* LDRBT rd, [rn], -imm */ \ + printf("LDRBT rd, [rn], -imm\n"); \ arm_access_memory(load, down, post, u8, imm); \ break; \ \ case 0x48: \ - /* STR rd, [rn], +imm */ \ + printf("STR rd, [rn], +imm\n"); \ arm_access_memory(store, up, post, u32, imm); \ break; \ \ case 0x49: \ - /* LDR rd, [rn], +imm */ \ + printf("LDR rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, u32, imm); \ break; \ \ case 0x4A: \ - /* STRT rd, [rn], +imm */ \ + printf("STRT rd, [rn], +imm\n"); \ arm_access_memory(store, up, post, u32, imm); \ break; \ \ case 0x4B: \ - /* LDRT rd, [rn], +imm */ \ + printf("LDRT rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, u32, imm); \ break; \ \ case 0x4C: \ - /* STRB rd, [rn], +imm */ \ + printf("STRB rd, [rn], +imm\n"); \ arm_access_memory(store, up, post, u8, imm); \ break; \ \ case 0x4D: \ - /* LDRB rd, [rn], +imm */ \ + printf("LDRB rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, u8, imm); \ break; \ \ case 0x4E: \ - /* STRBT rd, [rn], +imm */ \ + printf("STRBT rd, [rn], +imm\n"); \ arm_access_memory(store, up, post, u8, imm); \ break; \ \ case 0x4F: \ - /* LDRBT rd, [rn], +imm */ \ + printf("LDRBT rd, [rn], +imm\n"); \ arm_access_memory(load, up, post, u8, imm); \ break; \ \ case 0x50: \ - /* STR rd, [rn - imm] */ \ + printf("STR rd, [rn - imm]\n"); \ arm_access_memory(store, down, pre, u32, imm); \ break; \ \ case 0x51: \ - /* LDR rd, [rn - imm] */ \ + printf("LDR rd, [rn - imm]\n"); \ arm_access_memory(load, down, pre, u32, imm); \ break; \ \ case 0x52: \ - /* STR rd, [rn - imm]! */ \ + printf("STR rd, [rn - imm]!\n"); \ arm_access_memory(store, down, pre_wb, u32, imm); \ break; \ \ case 0x53: \ - /* LDR rd, [rn - imm]! */ \ + printf("LDR rd, [rn - imm]!\n"); \ arm_access_memory(load, down, pre_wb, u32, imm); \ break; \ \ case 0x54: \ - /* STRB rd, [rn - imm] */ \ + printf("STRB rd, [rn - imm]\n"); \ arm_access_memory(store, down, pre, u8, imm); \ break; \ \ case 0x55: \ - /* LDRB rd, [rn - imm] */ \ + printf("LDRB rd, [rn - imm]\n"); \ arm_access_memory(load, down, pre, u8, imm); \ break; \ \ case 0x56: \ - /* STRB rd, [rn - imm]! */ \ + printf("STRB rd, [rn - imm]!\n"); \ arm_access_memory(store, down, pre_wb, u8, imm); \ break; \ \ case 0x57: \ - /* LDRB rd, [rn - imm]! */ \ + printf("LDRB rd, [rn - imm]!\n"); \ arm_access_memory(load, down, pre_wb, u8, imm); \ break; \ \ case 0x58: \ - /* STR rd, [rn + imm] */ \ + printf("STR rd, [rn + imm]\n"); \ arm_access_memory(store, up, pre, u32, imm); \ break; \ \ case 0x59: \ - /* LDR rd, [rn + imm] */ \ + printf("LDR rd, [rn + imm]\n"); \ arm_access_memory(load, up, pre, u32, imm); \ break; \ \ case 0x5A: \ - /* STR rd, [rn + imm]! */ \ + printf("STR rd, [rn + imm]!\n"); \ arm_access_memory(store, up, pre_wb, u32, imm); \ break; \ \ case 0x5B: \ - /* LDR rd, [rn + imm]! */ \ + printf("LDR rd, [rn + imm]!\n"); \ arm_access_memory(load, up, pre_wb, u32, imm); \ break; \ \ case 0x5C: \ - /* STRB rd, [rn + imm] */ \ + printf("STRB rd, [rn + imm]\n"); \ arm_access_memory(store, up, pre, u8, imm); \ break; \ \ case 0x5D: \ - /* LDRB rd, [rn + imm] */ \ + printf("LDRB rd, [rn + imm]\n"); \ arm_access_memory(load, up, pre, u8, imm); \ break; \ \ case 0x5E: \ - /* STRB rd, [rn + imm]! */ \ + printf("STRB rd, [rn + imm]!\n"); \ arm_access_memory(store, up, pre_wb, u8, imm); \ break; \ \ case 0x5F: \ - /* LDRBT rd, [rn + imm]! */ \ + printf("LDRBT rd, [rn + imm]!\n"); \ arm_access_memory(load, up, pre_wb, u8, imm); \ break; \ \ case 0x60: \ - /* STR rd, [rn], -rm */ \ + printf("STR rd, [rn], -rm\n"); \ arm_access_memory(store, down, post, u32, reg); \ break; \ \ case 0x61: \ - /* LDR rd, [rn], -rm */ \ + printf("LDR rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, u32, reg); \ break; \ \ case 0x62: \ - /* STRT rd, [rn], -rm */ \ + printf("STRT rd, [rn], -rm\n"); \ arm_access_memory(store, down, post, u32, reg); \ break; \ \ case 0x63: \ - /* LDRT rd, [rn], -rm */ \ + printf("LDRT rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, u32, reg); \ break; \ \ case 0x64: \ - /* STRB rd, [rn], -rm */ \ + printf("STRB rd, [rn], -rm\n"); \ arm_access_memory(store, down, post, u8, reg); \ break; \ \ case 0x65: \ - /* LDRB rd, [rn], -rm */ \ + printf("LDRB rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, u8, reg); \ break; \ \ case 0x66: \ - /* STRBT rd, [rn], -rm */ \ + printf("STRBT rd, [rn], -rm\n"); \ arm_access_memory(store, down, post, u8, reg); \ break; \ \ case 0x67: \ - /* LDRBT rd, [rn], -rm */ \ + printf("LDRBT rd, [rn], -rm\n"); \ arm_access_memory(load, down, post, u8, reg); \ break; \ \ case 0x68: \ - /* STR rd, [rn], +rm */ \ + printf("STR rd, [rn], +rm\n"); \ arm_access_memory(store, up, post, u32, reg); \ break; \ \ case 0x69: \ - /* LDR rd, [rn], +rm */ \ + printf("LDR rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, u32, reg); \ break; \ \ case 0x6A: \ - /* STRT rd, [rn], +rm */ \ + printf("STRT rd, [rn], +rm\n"); \ arm_access_memory(store, up, post, u32, reg); \ break; \ \ case 0x6B: \ - /* LDRT rd, [rn], +rm */ \ + printf("LDRT rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, u32, reg); \ break; \ \ case 0x6C: \ - /* STRB rd, [rn], +rm */ \ + printf("STRB rd, [rn], +rm\n"); \ arm_access_memory(store, up, post, u8, reg); \ break; \ \ case 0x6D: \ - /* LDRB rd, [rn], +rm */ \ + printf("LDRB rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, u8, reg); \ break; \ \ case 0x6E: \ - /* STRBT rd, [rn], +rm */ \ + printf("STRBT rd, [rn], +rm\n"); \ arm_access_memory(store, up, post, u8, reg); \ break; \ \ case 0x6F: \ - /* LDRBT rd, [rn], +rm */ \ + printf("LDRBT rd, [rn], +rm\n"); \ arm_access_memory(load, up, post, u8, reg); \ break; \ \ case 0x70: \ - /* STR rd, [rn - rm] */ \ + printf("STR rd, [rn - rm]\n"); \ arm_access_memory(store, down, pre, u32, reg); \ break; \ \ case 0x71: \ - /* LDR rd, [rn - rm] */ \ + printf("LDR rd, [rn - rm]\n"); \ arm_access_memory(load, down, pre, u32, reg); \ break; \ \ case 0x72: \ - /* STR rd, [rn - rm]! */ \ + printf("STR rd, [rn - rm]!\n"); \ arm_access_memory(store, down, pre_wb, u32, reg); \ break; \ \ case 0x73: \ - /* LDR rd, [rn - rm]! */ \ + printf("LDR rd, [rn - rm]!\n"); \ arm_access_memory(load, down, pre_wb, u32, reg); \ break; \ \ case 0x74: \ - /* STRB rd, [rn - rm] */ \ + printf("STRB rd, [rn - rm]\n"); \ arm_access_memory(store, down, pre, u8, reg); \ break; \ \ case 0x75: \ - /* LDRB rd, [rn - rm] */ \ + printf("LDRB rd, [rn - rm]\n"); \ arm_access_memory(load, down, pre, u8, reg); \ break; \ \ case 0x76: \ - /* STRB rd, [rn - rm]! */ \ + printf("STRB rd, [rn - rm]!\n"); \ arm_access_memory(store, down, pre_wb, u8, reg); \ break; \ \ case 0x77: \ - /* LDRB rd, [rn - rm]! */ \ + printf("LDRB rd, [rn - rm]!\n"); \ arm_access_memory(load, down, pre_wb, u8, reg); \ break; \ \ case 0x78: \ - /* STR rd, [rn + rm] */ \ + printf("STR rd, [rn + rm]\n"); \ arm_access_memory(store, up, pre, u32, reg); \ break; \ \ case 0x79: \ - /* LDR rd, [rn + rm] */ \ + printf("LDR rd, [rn + rm]\n"); \ arm_access_memory(load, up, pre, u32, reg); \ break; \ \ case 0x7A: \ - /* STR rd, [rn + rm]! */ \ + printf("STR rd, [rn + rm]!\n"); \ arm_access_memory(store, up, pre_wb, u32, reg); \ break; \ \ case 0x7B: \ - /* LDR rd, [rn + rm]! */ \ + printf("LDR rd, [rn + rm]!\n"); \ arm_access_memory(load, up, pre_wb, u32, reg); \ break; \ \ case 0x7C: \ - /* STRB rd, [rn + rm] */ \ + printf("STRB rd, [rn + rm]\n"); \ arm_access_memory(store, up, pre, u8, reg); \ break; \ \ case 0x7D: \ - /* LDRB rd, [rn + rm] */ \ + printf("LDRB rd, [rn + rm]\n"); \ arm_access_memory(load, up, pre, u8, reg); \ break; \ \ case 0x7E: \ - /* STRB rd, [rn + rm]! */ \ + printf("STRB rd, [rn + rm]!\n"); \ arm_access_memory(store, up, pre_wb, u8, reg); \ break; \ \ case 0x7F: \ - /* LDRBT rd, [rn + rm]! */ \ + printf("LDRBT rd, [rn + rm]!\n"); \ arm_access_memory(load, up, pre_wb, u8, reg); \ break; \ \ case 0x80: \ - /* STMDA rn, rlist */ \ + printf("STMDA rn, rlist\n"); \ arm_block_memory(store, down_a, no, no); \ break; \ \ case 0x81: \ - /* LDMDA rn, rlist */ \ + printf("LDMDA rn, rlist\n"); \ arm_block_memory(load, down_a, no, no); \ break; \ \ case 0x82: \ - /* STMDA rn!, rlist */ \ + printf("STMDA rn!, rlist\n"); \ arm_block_memory(store, down_a, down, no); \ break; \ \ case 0x83: \ - /* LDMDA rn!, rlist */ \ + printf("LDMDA rn!, rlist\n"); \ arm_block_memory(load, down_a, down, no); \ break; \ \ case 0x84: \ - /* STMDA rn, rlist^ */ \ + printf("STMDA rn, rlist^\n"); \ arm_block_memory(store, down_a, no, yes); \ break; \ \ case 0x85: \ - /* LDMDA rn, rlist^ */ \ + printf("LDMDA rn, rlist^\n"); \ arm_block_memory(load, down_a, no, yes); \ break; \ \ case 0x86: \ - /* STMDA rn!, rlist^ */ \ + printf("STMDA rn!, rlist^\n"); \ arm_block_memory(store, down_a, down, yes); \ break; \ \ case 0x87: \ - /* LDMDA rn!, rlist^ */ \ + printf("LDMDA rn!, rlist^\n"); \ arm_block_memory(load, down_a, down, yes); \ break; \ \ case 0x88: \ - /* STMIA rn, rlist */ \ + printf("STMIA rn, rlist\n"); \ arm_block_memory(store, no, no, no); \ break; \ \ case 0x89: \ - /* LDMIA rn, rlist */ \ + printf("LDMIA rn, rlist\n"); \ arm_block_memory(load, no, no, no); \ break; \ \ case 0x8A: \ - /* STMIA rn!, rlist */ \ + printf("STMIA rn!, rlist\n"); \ arm_block_memory(store, no, up, no); \ break; \ \ case 0x8B: \ - /* LDMIA rn!, rlist */ \ + printf("LDMIA rn!, rlist\n"); \ arm_block_memory(load, no, up, no); \ break; \ \ case 0x8C: \ - /* STMIA rn, rlist^ */ \ + printf("STMIA rn, rlist^\n"); \ arm_block_memory(store, no, no, yes); \ break; \ \ case 0x8D: \ - /* LDMIA rn, rlist^ */ \ + printf("LDMIA rn, rlist^\n"); \ arm_block_memory(load, no, no, yes); \ break; \ \ case 0x8E: \ - /* STMIA rn!, rlist^ */ \ + printf("STMIA rn!, rlist^\n"); \ arm_block_memory(store, no, up, yes); \ break; \ \ case 0x8F: \ - /* LDMIA rn!, rlist^ */ \ + printf("LDMIA rn!, rlist^\n"); \ arm_block_memory(load, no, up, yes); \ break; \ \ case 0x90: \ - /* STMDB rn, rlist */ \ + printf("STMDB rn, rlist\n"); \ arm_block_memory(store, down_b, no, no); \ break; \ \ case 0x91: \ - /* LDMDB rn, rlist */ \ + printf("LDMDB rn, rlist\n"); \ arm_block_memory(load, down_b, no, no); \ break; \ \ case 0x92: \ - /* STMDB rn!, rlist */ \ + printf("STMDB rn!, rlist\n"); \ arm_block_memory(store, down_b, down, no); \ break; \ \ case 0x93: \ - /* LDMDB rn!, rlist */ \ + printf("LDMDB rn!, rlist\n"); \ arm_block_memory(load, down_b, down, no); \ break; \ \ case 0x94: \ - /* STMDB rn, rlist^ */ \ + printf("STMDB rn, rlist^\n"); \ arm_block_memory(store, down_b, no, yes); \ break; \ \ case 0x95: \ - /* LDMDB rn, rlist^ */ \ + printf("LDMDB rn, rlist^\n"); \ arm_block_memory(load, down_b, no, yes); \ break; \ \ case 0x96: \ - /* STMDB rn!, rlist^ */ \ + printf("STMDB rn!, rlist^\n"); \ arm_block_memory(store, down_b, down, yes); \ break; \ \ case 0x97: \ - /* LDMDB rn!, rlist^ */ \ + printf("LDMDB rn!, rlist^\n"); \ arm_block_memory(load, down_b, down, yes); \ break; \ \ case 0x98: \ - /* STMIB rn, rlist */ \ + printf("STMIB rn, rlist\n"); \ arm_block_memory(store, up, no, no); \ break; \ \ case 0x99: \ - /* LDMIB rn, rlist */ \ + printf("LDMIB rn, rlist\n"); \ arm_block_memory(load, up, no, no); \ break; \ \ case 0x9A: \ - /* STMIB rn!, rlist */ \ + printf("STMIB rn!, rlist\n"); \ arm_block_memory(store, up, up, no); \ break; \ \ case 0x9B: \ - /* LDMIB rn!, rlist */ \ + printf("LDMIB rn!, rlist\n"); \ arm_block_memory(load, up, up, no); \ break; \ \ case 0x9C: \ - /* STMIB rn, rlist^ */ \ + printf("STMIB rn, rlist^\n"); \ arm_block_memory(store, up, no, yes); \ break; \ \ case 0x9D: \ - /* LDMIB rn, rlist^ */ \ + printf("LDMIB rn, rlist^\n"); \ arm_block_memory(load, up, no, yes); \ break; \ \ case 0x9E: \ - /* STMIB rn!, rlist^ */ \ + printf("STMIB rn!, rlist^\n"); \ arm_block_memory(store, up, up, yes); \ break; \ \ case 0x9F: \ - /* LDMIB rn!, rlist^ */ \ + printf("LDMIB rn!, rlist^\n"); \ arm_block_memory(load, up, up, yes); \ break; \ \ case 0xA0 ... 0xAF: \ { \ - /* B offset */ \ + printf("B offset\n"); \ arm_b(); \ break; \ } \ \ case 0xB0 ... 0xBF: \ { \ - /* BL offset */ \ + printf("BL offset\n"); \ arm_bl(); \ break; \ } \ @@ -1725,11 +1725,11 @@ void translate_icache_sync() { { \ u32 swinum = (opcode >> 16) & 0xFF; \ if (swinum == 6) { \ - cycle_count += 64; /* Big under-estimation here */ \ + cycle_count += 64; printf("Big under-estimation here\n"); \ arm_hle_div(arm); \ } \ else if (swinum == 7) { \ - cycle_count += 64; /* Big under-estimation here */ \ + cycle_count += 64; printf("Big under-estimation here\n"); \ arm_hle_div_arm(arm); \ } \ else { \ @@ -1750,45 +1750,45 @@ void translate_icache_sync() { opcode = readaddress16(pc_address_block, (pc & 0x7FFF)); \ emit_trace_thumb_instruction(pc); \ u8 hiop = opcode >> 8; \ - \ + printf("%x: %04x ", pc, opcode); \ switch(hiop) \ { \ case 0x00 ... 0x07: \ - /* LSL rd, rs, imm */ \ + printf("LSL rd, rs, imm\n"); \ thumb_shift(shift, lsl, imm); \ break; \ \ case 0x08 ... 0x0F: \ - /* LSR rd, rs, imm */ \ + printf("LSR rd, rs, imm\n"); \ thumb_shift(shift, lsr, imm); \ break; \ \ case 0x10 ... 0x17: \ - /* ASR rd, rs, imm */ \ + printf("ASR rd, rs, imm\n"); \ thumb_shift(shift, asr, imm); \ break; \ \ case 0x18 ... 0x19: \ - /* ADD rd, rs, rn */ \ + printf("ADD rd, rs, rn\n"); \ thumb_data_proc(add_sub, adds, reg, rd, rs, rn); \ break; \ \ case 0x1A ... 0x1B: \ - /* SUB rd, rs, rn */ \ + printf("SUB rd, rs, rn\n"); \ thumb_data_proc(add_sub, subs, reg, rd, rs, rn); \ break; \ \ case 0x1C ... 0x1D: \ - /* ADD rd, rs, imm */ \ + printf("ADD rd, rs, imm\n"); \ thumb_data_proc(add_sub_imm, adds, imm, rd, rs, imm); \ break; \ \ case 0x1E ... 0x1F: \ - /* SUB rd, rs, imm */ \ + printf("SUB rd, rs, imm\n"); \ thumb_data_proc(add_sub_imm, subs, imm, rd, rs, imm); \ break; \ \ - /* MOV r0..7, imm */ \ + printf("MOV r0..7, imm\n"); \ case 0x20: thumb_data_proc_unary(imm, movs, imm, 0, imm); break; \ case 0x21: thumb_data_proc_unary(imm, movs, imm, 1, imm); break; \ case 0x22: thumb_data_proc_unary(imm, movs, imm, 2, imm); break; \ @@ -1798,7 +1798,7 @@ void translate_icache_sync() { case 0x26: thumb_data_proc_unary(imm, movs, imm, 6, imm); break; \ case 0x27: thumb_data_proc_unary(imm, movs, imm, 7, imm); break; \ \ - /* CMP r0, imm */ \ + printf("CMP r0, imm\n"); \ case 0x28: thumb_data_proc_test(imm, cmp, imm, 0, imm); break; \ case 0x29: thumb_data_proc_test(imm, cmp, imm, 1, imm); break; \ case 0x2A: thumb_data_proc_test(imm, cmp, imm, 2, imm); break; \ @@ -1808,7 +1808,7 @@ void translate_icache_sync() { case 0x2E: thumb_data_proc_test(imm, cmp, imm, 6, imm); break; \ case 0x2F: thumb_data_proc_test(imm, cmp, imm, 7, imm); break; \ \ - /* ADD r0..7, imm */ \ + printf("ADD r0..7, imm\n"); \ case 0x30: thumb_data_proc(imm, adds, imm, 0, 0, imm); break; \ case 0x31: thumb_data_proc(imm, adds, imm, 1, 1, imm); break; \ case 0x32: thumb_data_proc(imm, adds, imm, 2, 2, imm); break; \ @@ -1818,7 +1818,7 @@ void translate_icache_sync() { case 0x36: thumb_data_proc(imm, adds, imm, 6, 6, imm); break; \ case 0x37: thumb_data_proc(imm, adds, imm, 7, 7, imm); break; \ \ - /* SUB r0..7, imm */ \ + printf("SUB r0..7, imm\n"); \ case 0x38: thumb_data_proc(imm, subs, imm, 0, 0, imm); break; \ case 0x39: thumb_data_proc(imm, subs, imm, 1, 1, imm); break; \ case 0x3A: thumb_data_proc(imm, subs, imm, 2, 2, imm); break; \ @@ -1832,22 +1832,22 @@ void translate_icache_sync() { switch((opcode >> 6) & 0x03) \ { \ case 0x00: \ - /* AND rd, rs */ \ + printf("AND rd, rs\n"); \ thumb_data_proc(alu_op, ands, reg, rd, rd, rs); \ break; \ \ case 0x01: \ - /* EOR rd, rs */ \ + printf("EOR rd, rs\n"); \ thumb_data_proc(alu_op, eors, reg, rd, rd, rs); \ break; \ \ case 0x02: \ - /* LSL rd, rs */ \ + printf("LSL rd, rs\n"); \ thumb_shift(alu_op, lsl, reg); \ break; \ \ case 0x03: \ - /* LSR rd, rs */ \ + printf("LSR rd, rs\n"); \ thumb_shift(alu_op, lsr, reg); \ break; \ } \ @@ -1857,22 +1857,22 @@ void translate_icache_sync() { switch((opcode >> 6) & 0x03) \ { \ case 0x00: \ - /* ASR rd, rs */ \ + printf("ASR rd, rs\n"); \ thumb_shift(alu_op, asr, reg); \ break; \ \ case 0x01: \ - /* ADC rd, rs */ \ + printf("ADC rd, rs\n"); \ thumb_data_proc(alu_op, adcs, reg, rd, rd, rs); \ break; \ \ case 0x02: \ - /* SBC rd, rs */ \ + printf("SBC rd, rs\n"); \ thumb_data_proc(alu_op, sbcs, reg, rd, rd, rs); \ break; \ \ case 0x03: \ - /* ROR rd, rs */ \ + printf("ROR rd, rs\n"); \ thumb_shift(alu_op, ror, reg); \ break; \ } \ @@ -1882,22 +1882,22 @@ void translate_icache_sync() { switch((opcode >> 6) & 0x03) \ { \ case 0x00: \ - /* TST rd, rs */ \ + printf("TST rd, rs\n"); \ thumb_data_proc_test(alu_op, tst, reg, rd, rs); \ break; \ \ case 0x01: \ - /* NEG rd, rs */ \ + printf("NEG rd, rs\n"); \ thumb_data_proc_unary(alu_op, neg, reg, rd, rs); \ break; \ \ case 0x02: \ - /* CMP rd, rs */ \ + printf("CMP rd, rs\n"); \ thumb_data_proc_test(alu_op, cmp, reg, rd, rs); \ break; \ \ case 0x03: \ - /* CMN rd, rs */ \ + printf("CMN rd, rs\n"); \ thumb_data_proc_test(alu_op, cmn, reg, rd, rs); \ break; \ } \ @@ -1907,55 +1907,55 @@ void translate_icache_sync() { switch((opcode >> 6) & 0x03) \ { \ case 0x00: \ - /* ORR rd, rs */ \ + printf("ORR rd, rs\n"); \ thumb_data_proc(alu_op, orrs, reg, rd, rd, rs); \ break; \ \ case 0x01: \ - /* MUL rd, rs */ \ + printf("MUL rd, rs\n"); \ thumb_data_proc(alu_op, muls, reg, rd, rs, rd); \ cycle_count += 2; /* Between 1 and 4 extra cycles */ \ break; \ \ case 0x02: \ - /* BIC rd, rs */ \ + printf("BIC rd, rs\n"); \ thumb_data_proc(alu_op, bics, reg, rd, rd, rs); \ break; \ \ case 0x03: \ - /* MVN rd, rs */ \ + printf("MVN rd, rs\n"); \ thumb_data_proc_unary(alu_op, mvns, reg, rd, rs); \ break; \ } \ break; \ \ case 0x44: \ - /* ADD rd, rs */ \ + printf("ADD rd, rs\n"); \ thumb_data_proc_hi(add); \ break; \ \ case 0x45: \ - /* CMP rd, rs */ \ + printf("CMP rd, rs\n"); \ thumb_data_proc_test_hi(cmp); \ break; \ \ case 0x46: \ - /* MOV rd, rs */ \ + printf("MOV rd, rs\n"); \ thumb_data_proc_mov_hi(); \ break; \ \ case 0x47: \ - /* BX rs */ \ + printf("BX rs\n"); \ thumb_bx(); \ break; \ \ case 0x48 ... 0x4F: \ - /* LDR r0..7, [pc + imm] */ \ + printf("LDR r0..7, [pc + imm]\n"); \ { \ thumb_decode_imm(); \ u32 rdreg = (hiop & 7); \ u32 aoff = (pc & ~2) + (imm*4) + 4; \ - /* ROM + same page -> optimize as const load */ \ + printf("ROM + same page -> optimize as const load\n"); \ if (!ram_region && (((aoff + 4) >> 15) == (pc >> 15))) { \ u32 value = readaddress32(pc_address_block, (aoff & 0x7FFF)); \ thumb_load_pc_pool_const(rdreg, value); \ @@ -1966,78 +1966,78 @@ void translate_icache_sync() { break; \ \ case 0x50 ... 0x51: \ - /* STR rd, [rb + ro] */ \ + printf("STR rd, [rb + ro]\n"); \ thumb_access_memory(store, mem_reg, rd, rb, ro, reg_reg, 0, u32); \ break; \ \ case 0x52 ... 0x53: \ - /* STRH rd, [rb + ro] */ \ + printf("STRH rd, [rb + ro]\n"); \ thumb_access_memory(store, mem_reg, rd, rb, ro, reg_reg, 0, u16); \ break; \ \ case 0x54 ... 0x55: \ - /* STRB rd, [rb + ro] */ \ + printf("STRB rd, [rb + ro]\n"); \ thumb_access_memory(store, mem_reg, rd, rb, ro, reg_reg, 0, u8); \ break; \ \ case 0x56 ... 0x57: \ - /* LDSB rd, [rb + ro] */ \ + printf("LDSB rd, [rb + ro]\n"); \ thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, s8); \ break; \ \ case 0x58 ... 0x59: \ - /* LDR rd, [rb + ro] */ \ + printf("LDR rd, [rb + ro]\n"); \ thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, u32); \ break; \ \ case 0x5A ... 0x5B: \ - /* LDRH rd, [rb + ro] */ \ + printf("LDRH rd, [rb + ro]\n"); \ thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, u16); \ break; \ \ case 0x5C ... 0x5D: \ - /* LDRB rd, [rb + ro] */ \ + printf("LDRB rd, [rb + ro]\n"); \ thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, u8); \ break; \ \ case 0x5E ... 0x5F: \ - /* LDSH rd, [rb + ro] */ \ + printf("LDSH rd, [rb + ro]\n"); \ thumb_access_memory(load, mem_reg, rd, rb, ro, reg_reg, 0, s16); \ break; \ \ case 0x60 ... 0x67: \ - /* STR rd, [rb + imm] */ \ + printf("STR rd, [rb + imm]\n"); \ thumb_access_memory(store, mem_imm, rd, rb, 0, reg_imm, (imm * 4), \ u32); \ break; \ \ case 0x68 ... 0x6F: \ - /* LDR rd, [rb + imm] */ \ + printf("LDR rd, [rb + imm]\n"); \ thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, (imm * 4), u32); \ break; \ \ case 0x70 ... 0x77: \ - /* STRB rd, [rb + imm] */ \ + printf("STRB rd, [rb + imm]\n"); \ thumb_access_memory(store, mem_imm, rd, rb, 0, reg_imm, imm, u8); \ break; \ \ case 0x78 ... 0x7F: \ - /* LDRB rd, [rb + imm] */ \ + printf("LDRB rd, [rb + imm]\n"); \ thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, imm, u8); \ break; \ \ case 0x80 ... 0x87: \ - /* STRH rd, [rb + imm] */ \ + printf("STRH rd, [rb + imm]\n"); \ thumb_access_memory(store, mem_imm, rd, rb, 0, reg_imm, \ (imm * 2), u16); \ break; \ \ case 0x88 ... 0x8F: \ - /* LDRH rd, [rb + imm] */ \ + printf("LDRH rd, [rb + imm]\n"); \ thumb_access_memory(load, mem_imm, rd, rb, 0, reg_imm, (imm * 2), u16); \ break; \ \ - /* STR r0..7, [sp + imm] */ \ + printf("STR r0..7, [sp + imm]\n"); \ case 0x90: \ thumb_access_memory(store, imm, 0, 13, 0, reg_imm_sp, imm, u32); \ break; \ @@ -2063,7 +2063,7 @@ void translate_icache_sync() { thumb_access_memory(store, imm, 7, 13, 0, reg_imm_sp, imm, u32); \ break; \ \ - /* LDR r0..7, [sp + imm] */ \ + printf("LDR r0..7, [sp + imm]\n"); \ case 0x98: \ thumb_access_memory(load, imm, 0, 13, 0, reg_imm_sp, imm, u32); \ break; \ @@ -2089,7 +2089,7 @@ void translate_icache_sync() { thumb_access_memory(load, imm, 7, 13, 0, reg_imm_sp, imm, u32); \ break; \ \ - /* ADD r0..7, pc, +imm */ \ + printf("ADD r0..7, pc, +imm\n"); \ case 0xA0: thumb_load_pc(0); break; \ case 0xA1: thumb_load_pc(1); break; \ case 0xA2: thumb_load_pc(2); break; \ @@ -2099,7 +2099,7 @@ void translate_icache_sync() { case 0xA6: thumb_load_pc(6); break; \ case 0xA7: thumb_load_pc(7); break; \ \ - /* ADD r0..7, sp, +imm */ \ + printf("ADD r0..7, sp, +imm\n"); \ case 0xA8: thumb_load_sp(0); break; \ case 0xA9: thumb_load_sp(1); break; \ case 0xAA: thumb_load_sp(2); break; \ @@ -2112,183 +2112,183 @@ void translate_icache_sync() { case 0xB0 ... 0xB3: \ if((opcode >> 7) & 0x01) \ { \ - /* ADD sp, -imm */ \ + printf("ADD sp, -imm\n"); \ thumb_adjust_sp(down); \ } \ else \ { \ - /* ADD sp, +imm */ \ + printf("ADD sp, +imm\n"); \ thumb_adjust_sp(up); \ } \ break; \ \ case 0xB4: \ - /* PUSH rlist */ \ + printf("PUSH rlist\n"); \ thumb_block_memory(store, down, no, 13); \ break; \ \ case 0xB5: \ - /* PUSH rlist, lr */ \ + printf("PUSH rlist, lr\n"); \ thumb_block_memory(store, push_lr, push_lr, 13); \ break; \ \ case 0xBC: \ - /* POP rlist */ \ + printf("POP rlist\n"); \ thumb_block_memory(load, no, up, 13); \ break; \ \ case 0xBD: \ - /* POP rlist, pc */ \ + printf("POP rlist, pc\n"); \ thumb_block_memory(load, no, pop_pc, 13); \ break; \ \ case 0xC0: \ - /* STMIA r0!, rlist */ \ + printf("STMIA r0!, rlist\n"); \ thumb_block_memory(store, no, up, 0); \ break; \ \ case 0xC1: \ - /* STMIA r1!, rlist */ \ + printf("STMIA r1!, rlist\n"); \ thumb_block_memory(store, no, up, 1); \ break; \ \ case 0xC2: \ - /* STMIA r2!, rlist */ \ + printf("STMIA r2!, rlist\n"); \ thumb_block_memory(store, no, up, 2); \ break; \ \ case 0xC3: \ - /* STMIA r3!, rlist */ \ + printf("STMIA r3!, rlist\n"); \ thumb_block_memory(store, no, up, 3); \ break; \ \ case 0xC4: \ - /* STMIA r4!, rlist */ \ + printf("STMIA r4!, rlist\n"); \ thumb_block_memory(store, no, up, 4); \ break; \ \ case 0xC5: \ - /* STMIA r5!, rlist */ \ + printf("STMIA r5!, rlist\n"); \ thumb_block_memory(store, no, up, 5); \ break; \ \ case 0xC6: \ - /* STMIA r6!, rlist */ \ + printf("STMIA r6!, rlist\n"); \ thumb_block_memory(store, no, up, 6); \ break; \ \ case 0xC7: \ - /* STMIA r7!, rlist */ \ + printf("STMIA r7!, rlist\n"); \ thumb_block_memory(store, no, up, 7); \ break; \ \ case 0xC8: \ - /* LDMIA r0!, rlist */ \ + printf("LDMIA r0!, rlist\n"); \ thumb_block_memory(load, no, up, 0); \ break; \ \ case 0xC9: \ - /* LDMIA r1!, rlist */ \ + printf("LDMIA r1!, rlist\n"); \ thumb_block_memory(load, no, up, 1); \ break; \ \ case 0xCA: \ - /* LDMIA r2!, rlist */ \ + printf("LDMIA r2!, rlist\n"); \ thumb_block_memory(load, no, up, 2); \ break; \ \ case 0xCB: \ - /* LDMIA r3!, rlist */ \ + printf("LDMIA r3!, rlist\n"); \ thumb_block_memory(load, no, up, 3); \ break; \ \ case 0xCC: \ - /* LDMIA r4!, rlist */ \ + printf("LDMIA r4!, rlist\n"); \ thumb_block_memory(load, no, up, 4); \ break; \ \ case 0xCD: \ - /* LDMIA r5!, rlist */ \ + printf("LDMIA r5!, rlist\n"); \ thumb_block_memory(load, no, up, 5); \ break; \ \ case 0xCE: \ - /* LDMIA r6!, rlist */ \ + printf("LDMIA r6!, rlist\n"); \ thumb_block_memory(load, no, up, 6); \ break; \ \ case 0xCF: \ - /* LDMIA r7!, rlist */ \ + printf("LDMIA r7!, rlist\n"); \ thumb_block_memory(load, no, up, 7); \ break; \ \ case 0xD0: \ - /* BEQ label */ \ + printf("BEQ label\n"); \ thumb_conditional_branch(eq); \ break; \ \ case 0xD1: \ - /* BNE label */ \ + printf("BNE label\n"); \ thumb_conditional_branch(ne); \ break; \ \ case 0xD2: \ - /* BCS label */ \ + printf("BCS label\n"); \ thumb_conditional_branch(cs); \ break; \ \ case 0xD3: \ - /* BCC label */ \ + printf("BCC label\n"); \ thumb_conditional_branch(cc); \ break; \ \ case 0xD4: \ - /* BMI label */ \ + printf("BMI label\n"); \ thumb_conditional_branch(mi); \ break; \ \ case 0xD5: \ - /* BPL label */ \ + printf("BPL label\n"); \ thumb_conditional_branch(pl); \ break; \ \ case 0xD6: \ - /* BVS label */ \ + printf("BVS label\n"); \ thumb_conditional_branch(vs); \ break; \ \ case 0xD7: \ - /* BVC label */ \ + printf("BVC label\n"); \ thumb_conditional_branch(vc); \ break; \ \ case 0xD8: \ - /* BHI label */ \ + printf("BHI label\n"); \ thumb_conditional_branch(hi); \ break; \ \ case 0xD9: \ - /* BLS label */ \ + printf("BLS label\n"); \ thumb_conditional_branch(ls); \ break; \ \ case 0xDA: \ - /* BGE label */ \ + printf("BGE label\n"); \ thumb_conditional_branch(ge); \ break; \ \ case 0xDB: \ - /* BLT label */ \ + printf("BLT label\n"); \ thumb_conditional_branch(lt); \ break; \ \ case 0xDC: \ - /* BGT label */ \ + printf("BGT label\n"); \ thumb_conditional_branch(gt); \ break; \ \ case 0xDD: \ - /* BLE label */ \ + printf("BLE label\n"); \ thumb_conditional_branch(le); \ break; \ \ @@ -2296,11 +2296,11 @@ void translate_icache_sync() { { \ u32 swinum = opcode & 0xFF; \ if (swinum == 6) { \ - cycle_count += 64; /* Big under-estimation here */ \ + cycle_count += 64; printf("Big under-estimation here\n"); \ arm_hle_div(thumb); \ } \ else if (swinum == 7) { \ - cycle_count += 64; /* Big under-estimation here */ \ + cycle_count += 64; printf("Big under-estimation here\n"); \ arm_hle_div_arm(thumb); \ } \ else { \ @@ -2311,24 +2311,24 @@ void translate_icache_sync() { \ case 0xE0 ... 0xE7: \ { \ - /* B label */ \ + printf("B label\n"); \ thumb_b(); \ break; \ } \ \ case 0xF0 ... 0xF7: \ { \ - /* (low word) BL label */ \ - /* This should possibly generate code if not in conjunction with a BLH \ - next, but I don't think anyone will do that. */ \ + printf("(low word) BL label\n"); \ + printf("This should possibly generate code if not in conjunction with a BLH \ + next, but I don't think anyone will do that.\n"); \ break; \ } \ \ case 0xF8 ... 0xFF: \ { \ - /* (high word) BL label */ \ - /* This might not be preceeding a BL low word (Golden Sun 2), if so \ - it must be handled like an indirect branch. */ \ + printf("(high word) BL label\n"); \ + printf("This might not be preceeding a BL low word (Golden Sun 2), if so \ + it must be handled like an indirect branch.\n"); \ if((last_opcode >= 0xF000) && (last_opcode < 0xF800)) \ { \ thumb_bl(); \ @@ -2369,7 +2369,7 @@ void translate_icache_sync() { u16 flag_status = 0; \ switch((opcode >> 8) & 0xFF) \ { \ - /* left shift by imm */ \ + printf("left shift by imm\n"); \ case 0x00 ... 0x07: \ thumb_flag_modifies_zn(); \ if(((opcode >> 6) & 0x1F) != 0) \ @@ -2378,22 +2378,22 @@ void translate_icache_sync() { } \ break; \ \ - /* right shift by imm */ \ + printf("right shift by imm\n"); \ case 0x08 ... 0x17: \ thumb_flag_modifies_znc(); \ break; \ \ - /* add, subtract */ \ + printf("add, subtract\n"); \ case 0x18 ... 0x1F: \ thumb_flag_modifies_all(); \ break; \ \ - /* mov reg, imm */ \ + printf("mov reg, imm\n"); \ case 0x20 ... 0x27: \ thumb_flag_modifies_zn(); \ break; \ \ - /* cmp reg, imm; add, subtract */ \ + printf("cmp reg, imm; add, subtract\n"); \ case 0x28 ... 0x3F: \ thumb_flag_modifies_all(); \ break; \ @@ -2402,22 +2402,22 @@ void translate_icache_sync() { switch((opcode >> 6) & 0x03) \ { \ case 0x00: \ - /* AND rd, rs */ \ + printf("AND rd, rs\n"); \ thumb_flag_modifies_zn(); \ break; \ \ case 0x01: \ - /* EOR rd, rs */ \ + printf("EOR rd, rs\n"); \ thumb_flag_modifies_zn(); \ break; \ \ case 0x02: \ - /* LSL rd, rs */ \ + printf("LSL rd, rs\n"); \ thumb_flag_modifies_zn_maybe_c(); \ break; \ \ case 0x03: \ - /* LSR rd, rs */ \ + printf("LSR rd, rs\n"); \ thumb_flag_modifies_zn_maybe_c(); \ break; \ } \ @@ -2427,41 +2427,41 @@ void translate_icache_sync() { switch((opcode >> 6) & 0x03) \ { \ case 0x00: \ - /* ASR rd, rs */ \ + printf("ASR rd, rs\n"); \ thumb_flag_modifies_zn_maybe_c(); \ break; \ \ case 0x01: \ - /* ADC rd, rs */ \ + printf("ADC rd, rs\n"); \ thumb_flag_modifies_all(); \ thumb_flag_requires_c(); \ break; \ \ case 0x02: \ - /* SBC rd, rs */ \ + printf("SBC rd, rs\n"); \ thumb_flag_modifies_all(); \ thumb_flag_requires_c(); \ break; \ \ case 0x03: \ - /* ROR rd, rs */ \ + printf("ROR rd, rs\n"); \ thumb_flag_modifies_zn_maybe_c(); \ break; \ } \ break; \ \ - /* TST, NEG, CMP, CMN */ \ + printf("TST, NEG, CMP, CMN\n"); \ case 0x42: \ thumb_flag_modifies_all(); \ break; \ \ - /* ORR, MUL, BIC, MVN */ \ + printf("ORR, MUL, BIC, MVN\n"); \ case 0x43: \ thumb_flag_modifies_zn(); \ break; \ \ case 0x45: \ - /* CMP rd, rs */ \ + printf("CMP rd, rs\n"); \ thumb_flag_modifies_all(); \ break; \ \