From 69c145be62173a908eeb8cf67f57bd7fdf499160 Mon Sep 17 00:00:00 2001
From: lif <>
Date: Tue, 26 Dec 2023 00:07:38 -0800
Subject: [PATCH] fix the pass-by-value of translation_ptr in
 emit_mem_access_loadop

---
 mips/mips_emit.h | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/mips/mips_emit.h b/mips/mips_emit.h
index ecffa37..d464604 100644
--- a/mips/mips_emit.h
+++ b/mips/mips_emit.h
@@ -633,8 +633,8 @@ u32 generate_load_rm_sh_##flags_op(u32 rm)                                    \
 u32 execute_spsr_restore_body(u32 address)
 {
   set_cpu_mode(cpu_modes[reg[REG_CPSR] & 0xF]);
-  if((io_registers[REG_IE] & io_registers[REG_IF]) &&
-   io_registers[REG_IME] && ((reg[REG_CPSR] & 0x80) == 0))
+  if((read_ioreg(REG_IE) & read_ioreg(REG_IF)) &&
+   read_ioreg(REG_IME) && ((reg[REG_CPSR] & 0x80) == 0))
   {
     REG_MODE(MODE_IRQ)[6] = address + 4;
     REG_SPSR(MODE_IRQ) = reg[REG_CPSR];
@@ -1178,8 +1178,8 @@ u32 execute_spsr_restore_body(u32 address)
 u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
 {
   set_cpu_mode(cpu_modes[_cpsr & 0xF]);
-  if((io_registers[REG_IE] & io_registers[REG_IF]) &&
-   io_registers[REG_IME] && ((_cpsr & 0x80) == 0))
+  if((read_ioreg(REG_IE) & read_ioreg(REG_IF)) &&
+   read_ioreg(REG_IME) && ((_cpsr & 0x80) == 0))
   {
     REG_MODE(MODE_IRQ)[6] = address + 4;
     REG_SPSR(MODE_IRQ) = _cpsr;
@@ -1856,6 +1856,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
 #ifdef TRACE_INSTRUCTIONS
   void trace_instruction(u32 pc, u32 mode)
   {
+  #ifndef NO_PRINT_ONLY_TRACE
     if (mode)
       printf("Executed arm %x\n", pc);
     else
@@ -1863,6 +1864,7 @@ u32 execute_store_cpsr_body(u32 _cpsr, u32 address)
     #ifdef TRACE_REGISTERS
     print_regs();
     #endif
+  #endif
   }
 
   #define emit_trace_instruction(pc, mode)                                      \
@@ -2115,9 +2117,10 @@ const u8 ldhldrtbl[11] = {0, 1, 2, 2, 3, 3, 4, 4, 4, 4, 5};
   (((u32*)ptr) - ((u32*)translation_ptr + 1))
 
 static void emit_mem_access_loadop(
-  u8 *translation_ptr,
+  u8 **ptranslation_ptr,
   u32 base_addr, unsigned size, unsigned alignment, bool signext)
 {
+#define translation_ptr (*ptranslation_ptr)
   switch (size) {
   case 2:
     mips_emit_lw(reg_rv, reg_rv, (base_addr & 0xffff));
@@ -2146,6 +2149,7 @@ static void emit_mem_access_loadop(
     }
     break;
   };
+#undef translation_ptr
 }
 
 #ifdef PIC
@@ -2316,8 +2320,8 @@ static void emit_pmemld_stub(
   }
 
   // Emit load operation
-  emit_mem_access_loadop(translation_ptr, base_addr, size, alignment, signext);
-  translation_ptr += 4;
+  emit_mem_access_loadop(&translation_ptr, base_addr, size, alignment, signext);
+  //translation_ptr += 4;
 
   if (!(alignment == 0 || (size == 1 && signext))) {
     // Unaligned accesses require rotation, except for size=1 & signext