diff --git a/arm/arm64_stub.S b/arm/arm64_stub.S index 2ccf74d..724f348 100644 --- a/arm/arm64_stub.S +++ b/arm/arm64_stub.S @@ -354,7 +354,7 @@ defsymbl(execute_arm_translate_internal) // Check whether the CPU is sleeping already, we should just wait for IRQs ldr w1, [reg_base, #CPU_HALT_STATE] - cbnz w1, alert_loop + cbnz w1, cpu_sleep_loop ldr w0, [reg_base, #REG_PC] // load current PC @@ -708,19 +708,18 @@ write_epilogue: ldr w0, [reg_base, #REG_PC] // load new PC tbz reg_save0, #CPU_ALERT_HALT_B, lookup_pc // Resume execution if running - // explicit fallthrough to alert_loop, while CPU is halted + // explicit fallthrough to cpu_sleep_loop, while CPU is halted -alert_loop: +cpu_sleep_loop: mov w0, reg_cycles // load remaining cycles bl update_gba // update GBA until CPU isn't halted - and reg_cycles, w0, 0x7fff // load new cycle count ldr w1, [reg_base, #COMPLETED_FRAME] // Check whether a frame was completed cbnz w1, return_to_main // and return to caller function. - ldr w1, [reg_base, #CPU_HALT_STATE] // Check whether the CPU is halted - cbnz w1, alert_loop // and keep looping until it is + // At this point the CPU must be active, otherwise we sping in update_gba + and reg_cycles, w0, 0x7fff // load new cycle count ldr w0, [reg_base, #REG_PC] // load new PC b lookup_pc // Resume execution at that PC diff --git a/arm/arm_stub.S b/arm/arm_stub.S index bb98cd9..7362a8e 100644 --- a/arm/arm_stub.S +++ b/arm/arm_stub.S @@ -437,7 +437,7 @@ defsymbl(execute_arm_translate_internal) @ Check whether the CPU is sleeping already, we should just wait for IRQs ldr r1, [reg_base, #CPU_HALT_STATE] cmp r1, #0 - bne alert_loop + bne cpu_sleep_loop b lookup_pc @@ -692,11 +692,11 @@ write_epilogue: tst r2, #CPU_ALERT_HALT @ check for CPU halt bit beq lookup_pc @ Resume execution if not halted - @ Fallthrough to alert_loop on purpose (CPU is now halted) + @ Fallthrough to cpu_sleep_loop on purpose (CPU is now halted) mvn r0, reg_cycles @ setup for update_gba -alert_loop: +cpu_sleep_loop: call_c_function(update_gba) @ update GBA until CPU isn't halted bic r0, r0, #0x80000000 @ clear MSB, not part of count @@ -704,10 +704,7 @@ alert_loop: cmp r1, #0 bne return_to_main - ldr r1, [reg_base, #CPU_HALT_STATE] @ Check whether the CPU is halted - cmp r1, #0 - bne alert_loop @ Keep looping until it is - + @ The cpu is active again, go ahead and resume execution at current PC mvn reg_cycles, r0 @ load new cycle count ldr r0, [reg_base, #REG_PC] @ load new PC ldr r1, [reg_base, #REG_CPSR] @ r1 = flags diff --git a/mips/mips_stub.S b/mips/mips_stub.S index 399d913..46e8269 100644 --- a/mips/mips_stub.S +++ b/mips/mips_stub.S @@ -338,21 +338,18 @@ defsymbl(write_io_epilogue) andi $4, $19, CPU_ALERT_HALT # check if CPU is halted beqz $4, lookup_pc # continue running if not halted - # Purposely fallthrough to alert_loop, wait for CPU wakeup + # Purposely fallthrough to cpu_sleep_loop, wait for CPU wakeup -alert_loop: +cpu_sleep_loop: move $4, reg_cycles # Remaining cycles as asg0 cfncall update_gba, 0 # process the next event - and reg_cycles, $2, 0x7FFF # update new cycle count (ret value) lw $1, COMPLETED_FRAME($16) # Check whether we completed a frame bne $1, $0, return_to_main # Return to main thread now - lw $1, CPU_HALT_STATE($16) # check if CPU is sleeping - bne $1, $0, alert_loop # see if it hasn't changed - nop - + # since no frame was completed, this means CPU is active again. # Fall through to lookup_pc to resume execution + and reg_cycles, $2, 0x7FFF # update new cycle count (ret value) lookup_pc: extract_flags # $1 contains CPSR now @@ -536,7 +533,7 @@ defsymbl(execute_arm_translate_internal) # CPU might be sleeping, do not wake ip up! lw $1, CPU_HALT_STATE($16) # check if CPU is sleeping - bne $1, $0, alert_loop # see if it hasn't changed + bne $1, $0, cpu_sleep_loop # see if it hasn't changed lw $1, REG_CPSR($16) and $1, $1, 0x20 # see if Thumb bit is set in flags diff --git a/x86/x86_stub.S b/x86/x86_stub.S index b263b58..1a96654 100644 --- a/x86/x86_stub.S +++ b/x86/x86_stub.S @@ -242,7 +242,7 @@ ext_store_backup8: # Handle I/O write side-effects: # SMC: Flush RAM caches # IRQ: Perform CPU mode change -# HLT: spin in the alert_loop until an IRQ is triggered +# HLT: spin in the cpu_sleep_loop until an IRQ is triggered write_epilogue: mov %eax, REG_SAVE(REG_BASE)# Save ret value for later use collapse_flags # Consolidate CPSR @@ -259,25 +259,20 @@ write_epilogue: testl $CPU_ALERT_HALT, REG_SAVE(REG_BASE) # Check for CPU_ALERT_HALT bit jz lookup_pc # if not halt, continue executing - # explicit fallthrough to alert_loop, while CPU is halted + # explicit fallthrough to cpu_sleep_loop, while CPU is halted -alert_loop: +cpu_sleep_loop: mov REG_CYCLES, CARG1_REG # Load remaining cycles as arg0 CALL_FUNC(update_gba) # process the next event - mov %eax, REG_CYCLES # load new cycle count - and $0x7fff, REG_CYCLES # (only lowest bits) # did we just complete a frame? go back to main then cmpl $0, COMPLETED_FRAME(REG_BASE) jne return_to_main - # see if the halt status has changed - mov CPU_HALT_STATE(REG_BASE), %edx - - cmp $0, %edx # 0 means it has - jnz alert_loop # if not go again - - jmp lookup_pc # pc has definitely changed + // if we are out of update_gba and did not complete a frame, cpu is active + mov %eax, REG_CYCLES # load new cycle count + and $0x7fff, REG_CYCLES # (only lowest bits) + jmp lookup_pc # pc changes after a halt ext_store_eeprom: @@ -529,7 +524,7 @@ defsymbl(execute_arm_translate_internal) # loop in the alert loop until it wakes up) cmpl $0, CPU_HALT_STATE(REG_BASE) je 1f - call alert_loop # Need to push something to the stack + call cpu_sleep_loop # Need to push something to the stack 1: call lookup_pc # Go fetch and execute PC