diff --git a/gba_memory.c b/gba_memory.c
index ab6df9d..8a09fd0 100644
--- a/gba_memory.c
+++ b/gba_memory.c
@@ -238,7 +238,7 @@ static void trigger_timer(u32 timer_number, u32 value)
          timer[timer_number].prescale = prescale;
          timer[timer_number].irq = ((value >> 6) & 0x1);
 
-         write_ioreg(REG_TM0D + (timer_number * 2), (u32)(-timer_reload));
+         write_ioreg(REG_TMXD(timer_number), (u32)(-timer_reload));
 
          timer_reload <<= prescale;
          timer[timer_number].count = timer_reload;
@@ -265,7 +265,7 @@ static void trigger_timer(u32 timer_number, u32 value)
          timer[timer_number].status = TIMER_INACTIVE;
       }
    }
-   write_ioreg(REG_TM0CNT + (timer_number * 2), value);
+   write_ioreg(REG_TMXCNT(timer_number), value);
 }
 
 // This table is configured for sequential access on system defaults
diff --git a/gba_memory.h b/gba_memory.h
index 865711a..6c3be06 100644
--- a/gba_memory.h
+++ b/gba_memory.h
@@ -49,6 +49,10 @@ extern int use_libretro_save_method;
 #define DMA_DIRECT_SOUND_B            1
 #define DMA_NO_DIRECT_SOUND           2
 
+// Access to timer registers
+#define REG_TMXD(n)   (REG_TM0D   + (2 * (n)))
+#define REG_TMXCNT(n) (REG_TM0CNT + (2 * (n)))
+
 typedef struct
 {
   u32 source_address;
diff --git a/main.c b/main.c
index 8da907f..b99c112 100644
--- a/main.c
+++ b/main.c
@@ -51,7 +51,7 @@ static unsigned update_timers(irq_type *irq_raised, unsigned completed_cycles)
       {
          timer[i].count -= completed_cycles;
          /* io_registers accessors range: REG_TM0D, REG_TM1D, REG_TM2D, REG_TM3D */
-         write_ioreg(REG_TM0D + (i * 2), -(timer[i].count > timer[i].prescale));
+         write_ioreg(REG_TMXD(i), -(timer[i].count >> timer[i].prescale));
       }
 
       if(timer[i].count > 0)
@@ -59,12 +59,12 @@ static unsigned update_timers(irq_type *irq_raised, unsigned completed_cycles)
 
       /* irq_raised value range: IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3 */
       if(timer[i].irq)
-         *irq_raised |= (8 << i);
+         *irq_raised |= (IRQ_TIMER0 << i);
 
       if((i != 3) && (timer[i + 1].status == TIMER_CASCADE))
       {
          timer[i + 1].count--;
-         write_ioreg(REG_TM0D + (i + 1) * 2, -timer[i+1].count);
+         write_ioreg(REG_TMXD(i + 1), -timer[i+1].count);
       }
 
       if(i < 2)
@@ -253,10 +253,8 @@ u32 function_cc update_gba(int remaining_cycles)
 
     for (i = 0; i < 4; i++)
     {
-       if(timer[i].status != TIMER_PRESCALE)
-          continue;
-
-       if(timer[i].count < execute_cycles)
+       if (timer[i].status == TIMER_PRESCALE &&
+           timer[i].count < execute_cycles)
           execute_cycles = timer[i].count;
     }
   } while(reg[CPU_HALT_STATE] != CPU_ACTIVE && !reg[COMPLETED_FRAME]);